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Электронный компонент: SN65LVDS048A

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SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B SEPTEMBER 2000 REVISED SEPTEMBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
>400 Mbps (200 MHz) Signaling Rates
D
Flow-Through Pinout Simplifies PCB
Layout
D
50 ps Channel-to-Channel Skew (Typ)
D
200 ps Differential Skew (Typ)
D
Propagation Delay Times 2.7 ns (Typ)
D
3.3-V Power Supply Design
D
High Impedance LVDS Inputs on Power
Down
D
Low-Power Dissipation (40 mW at 3.3 V
Static)
D
Accepts Small Swing (350 mV) Differential
Signal Levels
D
Supports Open, Short, and Terminated
Input Fail-Safe
D
Industrial Operating Temperature Range
(40
C to 85
C)
D
Conforms to TIA/EIA-644 LVDS Standard
D
Available in SOIC and TSSOP Packages
D
Pin-Compatible With DS90LV048A From
National
description
The SN65LVDS048A is a quad differential line receiver
that implements the electrical characteristics of
low-voltage differential signaling (LVDS). This signaling
technique lowers the output voltage levels of 5-V
differential standard levels (such as EIA/TIA-422B) to
reduce the power, increase the switching speeds, and
allow operation with a 3.3-V supply rail. Any of the quad
differential receivers will provide a valid logical output state with a
100-mV differential input voltage within the
input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential
difference between two LVDS nodes.
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100
. The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to the environment, and other system characteristics.
The SN65LVDS048A is characterized for operation from 40
C to 85
C.
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
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5
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7
8
16
15
14
13
12
11
10
9
SN65LVDS048AD (Marked as LVDS048A)
SN65LVDS048APW (Marked as DL048A)
(TOP VIEW)
EN
R
OUT1
R
OUT2
V
CC
GND
R
OUT3
R
OUT4
EN
EN
EN
functional diagram
R
IN1+
R
IN1
R
IN2+
R
IN2
R
IN3+
R
IN3
R
IN4+
R
IN4
R
OUT4
R
OUT3
R
OUT2
R
OUT1
R1
R2
R3
R4
R
IN1
R
IN1+
R
IN2+
R
IN2
R
IN3
R
IN3+
R
IN4+
R
IN4
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B SEPTEMBER 2000 REVISED SEPTEMBER 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TRUTH TABLE
DIFFERENTIAL INPUT
ENABLES
OUTPUT
RIN+ RIN
EN
EN
ROUT
VID
100 mV
H
VID
100 mV
H
L or OPEN
L
Open/short or terminated
H
L or OPEN
H
X
All other conditions
Z
H = high level, L = low level, X = irrelevant, Z = high impedance (off)
equivalent input and output schematic diagrams
7 V
7 V
300 k
300 k
Input
Input
VCC
50
300 k
VCC
7 V
EN,EN
5
VCC
7 V
Output
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range (V
CC)
0.3 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(R
IN+
, R
IN
)
0.3 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable input voltage (EN, EN )
0.3 V to (V
CC
+0.3 V)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, V
O
(R
OUT
)
0.3 V to (V
CC
+0.3 V)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus-pin (R
IN+
, R
IN
) Electrostatic discharge (see Note 2)
> 10 kV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation
See Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA
25
C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25
C
TA = 85
C
POWER RATING
D
950 mW
7.6 mW/
C
494 mW
PW
774 mW
6.2 mW/
C
402 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B SEPTEMBER 2000 REVISED SEPTEMBER 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
3
3.3
3.6
V
Receiver input voltage
GND
3
V
Commonmode input voltage, VIC
|V
ID
|
2
2.4
*
|V
ID
|
2
V
VCC 0.8
Operating free-air temperature, TA
40
25
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Note 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIT+
Differential input high threshold voltage
VCM = 1.2 V, 0.05 V, 2.35 V
100
mV
VIT
Differential input low threshold voltage
VCM = 1.2 V, 0.05 V, 2.35 V
(see Note 4)
100
mV
V(CMR)
Common mode voltage range
VID = 200 mV pk to pk (see Note 5)
0.1
2.3
V
VIN = 2.8 V
V
3 6 V or 0 V
20
1
20
A
IIN
Input current
VIN = 0 V
VCC = 3.6 V or 0 V
20
1
20
A
IIN
In ut current
VIN = 3.6 V
VCC = 0 V
20
1
20
A
IOH = 0.4 mA, VID = 200 mV
2.7
3.2
V
VOH
Output high voltage
IOH = 0.4 mA, input terminated
2.7
3.2
V
VOH
Out ut high voltage
IOH = 0.4 mA, input shorted
2.7
3.2
V
VOL
Output low voltage
IOL = 2 mA, VID = 200 mV
0.05
0.25
V
IOS
Output short circuit current
Enabled, VOUT = 0 V (see Note 6)
65
100
mA
IO(Z)
Output 3-state current
Disabled, VOUT = 0 V or VCC
1
1
A
VIH
Input high voltage
2.0
VCC
V
VIL
Input low voltage
GND
0.8
V
II
Input current (enables)
VIN = 0 V or VCC,
Other input = VCC or GND
10
10
A
VIK
Input clamp voltage
ICL = 18 mA
1.5
0.8
V
ICC
No load supply current, receivers enabled
EN = VCC, Inputs open
8
15
mA
ICC(Z)
No load supply current, receivers disabled
EN = GND, Inputs open
0.6
1.5
mA
All typical values are at 25
C and with a 3.3-V supply.
NOTES:
3. Current into device pin is defined as positive. Current out of the device is defined as negative. All voltages are referenced to ground,
unless otherwise specified.
4. VCC is always higher than RIN+ and RIN voltage, RIN and RIN+ have a voltage range of 0.2 V to VCCVID/2. To be compliant with
ac specifications the common voltage range is 0.1 V to 2.3 V.
5. The VCMR range is reduced for larger VID, Example: If VID = 400 mV, the VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs
shorted is not supported over the common-mode range of 0 V to 2.4 V, but is supported only with inputs shorted and no external
common-mode voltage applied. A VID up to VCC0 V may be applied to the RIN+ and RIN inputs with the common-mode voltage
set to VCC/2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to 400 mV. Skew
specifications apply for 200 mV < VID < 800 mV over the common-mode range.
6. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be
shorted at a time. Do not exceed maximum junction temperature specification.
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B SEPTEMBER 2000 REVISED SEPTEMBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating conditions (unless otherwise noted) (see
Notes 7)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPHL
Differential propagation delay, high-to-low
1.9
2.7
3.7
ns
tPLH
Differential propagation delay, low-to-high
1.9
2.9
3.7
ns
tSK(p)
Differential pulse skew (tPHLD tPLHD) (see Note 8)
200
450
ps
tSK(o)
Differential channel-to-channel skew; same device (see Note 8)
CL = 15 pF
VID 200 mV
50
500
ps
tSK(pp)
Differential part-to-part skew (see Note 10)
VID = 200 mV
(see Figure 1 and 2 )
1
ns
tSK(lim) Differential part-to-part skew (see Note11)
(see Figure 1 and 2 )
1.5
ns
tr
Rise time
0.5
1
ns
tf
Fall time
0.5
1
ns
tPHZ
Disable time high to Z
8
9
ns
tPLZ
Disable time low to Z
RL = 2 K
CL 15 pF
6
8
ns
tPZH
Enable time Z to high
CL = 15 pF
(see Figure 3 and 4 )
8
10
ns
tPZL
Enable time Z to low
(see Figure 3 and 4 )
7
8
ns
f(MAX)
Maximum operating frequency (see Note 12)
All channels switching
200
250
MHz
All typical values are at 25
C and with a 3.3-V supply.
NOTES:
7. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50
, tr and tf (0% 100%)
3 ns for RIN.
8. tSK(p)|tPLH tPHL| is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
9. tSK(o) is the differential channel-to-channel skew of any event on the same device.
10. tSK(pp) is the differential part-to-part skew, and is defined as the difference between the minimum and the maximum specified
differential propagation delays. This specification applies to devices at the same VCC and within 5
C of each other within the
operating temperature range.
11. tsk(lim) part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to
devices over recommended operating temperature and voltage ranges, and across process distribution. tsk(lim) is defined as |Min
Max| differential propagation delay.
12. f(MAX) generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%,
VOD > 250 mV, all channels switching
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B SEPTEMBER 2000 REVISED SEPTEMBER 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Generator
50
50
RIN+
RIN
CL
ROUT
Receiver Enabled
R
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
OV Differential
VID = 200 mV
1.2 V
tPLH
tPHL
tr
tf
80%
80%
1.5 V
1.5 V
1.3 V
1.1 V
VOH
VOL
RIN
RIN+
ROUT
20%
20%
Figure 2. Receiver Propagation Delay and Transition Time Waveforms