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Электронный компонент: SN65LVDS3486

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Meet or Exceed the Requirements of ANSI
TIA/EIA-644 Standard
D
Operate With a Single 3.3-V Supply
D
Designed for Signaling Rate of up to
400 Mbps
D
Differential Input Thresholds
100 mV Max
D
Typical Propagation Delay Time of 2.1 ns
D
Power Dissipation 60 mW Typical Per
Receiver at 200 MHz
D
Bus-Terminal ESD Protection Exceeds 8 kV
D
Low-Voltage TTL (LVTTL) Logic Output
Levels
D
Pin Compatible With AM26LS32, MC3486,
and
A9637
D
Open-Circuit Fail-Safe
description
The SN55LVDS32, SN65LVDS32,
SN65LVDS3486, and SN65LVDS9637 are
differential line receivers that implement the
electrical characteristics of low-voltage differential
signaling (LVDS). This signaling technique lowers
the output voltage levels of 5-V differential
standard levels (such as EIA/TIA-422B) to reduce
the power, increase the switching speeds, and
allow operation with a 3.3-V supply rail. Any of the
four differential receivers provides a valid logical
output state with a
100-mV differential input
voltage within the input common-mode voltage
range. The input common-mode voltage range
allows 1 V of ground potential difference between
two LVDS nodes.
The intended application of these devices and
signaling technique is both point-to-point and
multidrop (one driver and multiple receivers) data
transmission over controlled impedance media of
approximately 100
. The transmission media
may be printed-circuit board traces, backplanes,
or cables. The ultimate rate and distance of
data transfer depends on the attenuation
characteristics of the media and the noise
coupling to the environment.
The SN65LVDS32, SN65LVDS3486, and
SN65LVDS9637 are characterized for operation
from - 40
C to 85
C. The SN55LVDS32 is
characterized for operation from - 55
C to 125
C.
Copyright
1997 - 2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
19
20
1
3
2
17
18
16
15
14
13
12
11
9
10
5
4
6
7
8
4A
4Y
NC
G
3Y
1Y
G
NC
2Y
2A
1A
1B
NC
V
4B
GND
NC
3B
3A
2B
SN55LVDS32FK
(TOP VIEW)
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1Y
G
2Y
2A
2B
GND
V
CC
4B
4A
4Y
G
3Y
3A
3B
SN55LVDS32 . . . J OR W
SN65LVDS32 . . . D OR PW
(Marked as LVDS32 or 65LVDS32)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1Y
1,2EN
2Y
2A
2B
GND
V
CC
4B
4A
4Y
3,4EN
3Y
3A
3B
SN65LVDS3486D (Marked as LVDS3486)
(TOP VIEW)
1
2
3
4
8
7
6
5
V
CC
1Y
2Y
GND
1A
1B
2A
2B
SN65LVDS9637D (Marked as DK637 or LVDS37)
SN65LVDS9637DGN (Marked as L37)
SN65LVDS9637DGK (Marked as AXF)
(TOP VIEW)
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PowerPAD is a trademark of Texas Instruments.
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
MSOP
CHIP CARRIER
CERAMIC DIP
FLAT PACK
TA
(D)
(PW)
MSOP
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
FLAT PACK
(W)
SN65LVDS32D
SN65LVDS32PW
--
--
--
--
-40
C to
SN65LVDS3486D
--
--
--
--
-40 C to
85
C
SN65LVDS9637D
SN65LVDS9637DGN
--
--
--
85 C
--
SN65LVDS9637DGK
--
--
--
-55
C to
125
C
--
--
--
SNJ55LVDS32FK
SNJ55LVDS32J
SNJ55LVDS32W
SN55LVDS32W
G
G
1A
1B
2A
2B
3A
3B
4A
4B
4
12
2
1
6
7
10
9
14
15
3
5
11
13
1Y
2Y
3Y
4Y
'LVDS32 logic diagram
(positive logic)
1A
1B
2A
2B
3A
3B
4A
4B
4
12
2
1
6
7
10
9
14
15
3
5
11
13
1Y
2Y
3Y
4Y
3,4EN
1,2EN
SN65LVDS3486D logic diagram
(positive logic)
1A
1B
2A
2B
8
7
6
5
2
3
1Y
2Y
SN65LVDS9637D logic diagram
(positive logic)
logic symbol
2Y
1Y
2B
2A
1B
1A
5
6
7
8
3
2
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
SN65LVDS9637
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
FUNCTION TABLE
FUNCTION TABLE
SN55LVDS32, SN65LVDS32
FUNCTION TABLE
SN65LVDS3486
DIFFERENTIAL INPUT
ENABLES
OUTPUT
DIFFERENTIAL INPUT
ENABLE
OUTPUT
DIFFERENTIAL INPUT
A, B
G
G
OUTPUT
Y
DIFFERENTIAL INPUT
A, B
ENABLE
EN
OUTPUT
Y
VID
100 mV
H
X
X
L
H
H
VID
100 mV
H
H
-100 mV < VID < 100 mV
H
X
X
L
?
?
-100 mV < VID < 100 mV
H
?
VID
-100 mV
H
X
X
L
L
L
VID
-100 mV
H
L
X
L
H
Z
X
L
Z
Open
H
X
X
L
H
H
Open
H
H
H = high level, L = low level, X = irrelevant, Z = high impedance (off),
? = indeterminate
H = high level, L = low level, X = irrelevant, Z = high
impedance (off), ? = indeterminate
logic symbols
EN
1
G
G
1A
1B
2A
2B
3A
3B
4A
4B
3
5
11
13
1Y
2Y
3Y
4Y
4
12
2
1
6
7
10
9
14
15
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EN
EN
4B
4A
3B
3A
3, 4EN
13
11
4Y
3Y
15
14
9
10
12
2Y
1Y
2B
2A
1B
1A
1, 2EN
7
6
1
2
4
5
3
SN65LVDS3486
SN55LVDS32, SN65LVDS32
FUNCTION TABLE
SN65LVDS9637
DIFFERENTIAL INPUT
A, B
OUTPUT
Y
VID
100 mV
H
-100 mV < VID < 100 mV
?
VID
-100 mV
L
Open
H
H = high level, L = low level, ? = indeterminate
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
equivalent input and output schematic diagrams
300 k
300 k
VCC
7 V
7 V
A Input
B Input
7 V
50
VCC
Input
VCC
5
7 V
Y Output
EQUIVALENT OF EACH A OR B INPUT
EQUIVALENT OF G, G, 1,2EN OR
3,4EN INPUTS
TYPICAL OF ALL OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
(see Note 1)
-0.5 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(enables and output)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(A or B)
-0.5 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation
See Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
_
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
_
C to 150
_
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA
25
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25
C
TA = 70
C
POWER RATING
TA = 85
C
POWER RATING
TA = 125
C
POWER RATING
D (8)
725 mW
5.8 mW/
C
464 mW
377 mW
--
D (16)
950 mW
7.6 mW/
C
608 mW
494 mW
--
DGK
425 mW
3.4 mW/
C
272 mW
221 mW
--
DGN
2.14 W
17.1 mW/
C
1.37 W
1.11 W
--
FK
1375 mW
11.0 mW/
C
880 mW
715 mW
275 mW
J
1375 mW
11.0 mW/
C
880 mW
715 mW
275 mW
PW (16)
774 mW
6.2 mW/
C
496 mW
402 mW
--
W
1000 mW
8.0 mW/
C
640 mW
520 mW
200 mW
This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
The PowerPAD
must be soldered to a thermal land on the printed-circuit board. See the application note PowerPAD Thermally Enhanced
Package (SLMA002)
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
3
3.3
3.6
V
High-level input voltage, VIH
G, G, 1,2EN, or 3,4EN
2
V
Low-level input voltage, VIL
G, G, 1,2EN, or 3,4EN
0.8
V
Magnitude of differential input voltage, |VID|
0.1
0.6
V
Common-mode input voltage, VIC (see Figure 1)
| V
ID
|
2
2.4
*
| V
ID
|
2
V
Common-mode input voltage, VIC (see Figure 1)
VCC - 0.8
V
Operating free-air temperature, TA
SN65 prefix
-40
85
C
Operating free-air temperature, TA
SN55 prefix
-55
125
C
Max at VCC = 3 V
Max at VCC > 3.15 V
Min
1
0.5
0
0
0.1
0.2
0.3
- Common-Mode Input V
oltage Range - V
1.5
2
COMMON-MODE INPUT VOLTAGE RANGE
vs
DIFFERENTIAL INPUT VOLTAGE
2.5
0.4
0.5
0.6
V
IC
VID - Differential Input Voltage - V
Figure 1. V
IC
Versus V
ID
and V
CC
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN55LVDS32 electrical characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VITH+
Positive-going differential input voltage threshold
See Figure 2, Table 1, and Note 2
100
mV
VITH-
Negative-going differential input voltage threshold
See Figure 2, Table 1, and Note 2
-100
mV
VOH
High-level output voltage
IOH = -8 mA
2.4
V
VOL
Low-level output voltage
IOL = 8 mA
0.4
V
ICC
Supply current
Enabled,
No load
10
18
mA
ICC
Supply current
Disabled
0.25
0.5
mA
II
Input current (A or B inputs)
VI = 0
-2
-10
-20
A
II
Input current (A or B inputs)
VI = 2.4 V
-1.2
-3
A
II(OFF)
Power-off input current (A or B inputs)
VCC = 0,
VI = 2.4 V
6
20
A
IIH
High-level input current (EN, G, or G inputs)
VIH = 2 V
10
A
IIL
Low-level input current (EN, G, or G inputs)
VIL = 0.8 V
10
A
IOZ
High-impedance output current
VO = 0 or VCC
12
A
All typical values are at TA = 25
C and with VCC = 3.3 V.
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going
differential input voltage threshold only.
NOTE 2: |VITH| = 200 mV for operation at -55
C
SN55LVDS32 switching characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
1.3
2.3
6
ns
tPHL
Propagation delay time, high-to-low-level output
1.4
2.2
6.1
ns
tsk(o)
Channel-to-channel output skew
CL = 10 pF, See Figure 3
0.1
ns
tr
Output signal rise time, 20% to 80%
CL = 10 pF, See Figure 3
0.6
ns
tf
Output signal fall time, 80% to 20%
0.7
ns
tPHZ
Propagation delay time, high-level-to-high-impedance output
6.5
12
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
See Figure 4
5.5
12
ns
tPZH
Propagation delay time, high-impedance-to-high-level output
See Figure 4
8
14
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
3
12
ns
tsk(o) is the maximum delay time difference between drivers on the same device.
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN65LVDSxxxx electrical characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN65LVDS32
SN65LVDS3486
SN65LVDS9637
UNIT
MIN
TYP
MAX
VIT+
Positive-going differential input voltage threshold
See Figure 2 and Table 1
100
mV
VIT-
Negative-going differential input voltage threshold
See Figure 2 and Table 1
-100
mV
VOH
High-level output voltage
IOH = -8 mA
2.4
V
VOH
High-level output voltage
IOH = -4 mA
2.8
V
VOL
Low-level output voltage
IOL = 8 mA
0.4
V
SN65LVDS32,
Enabled,
No load
10
18
ICC
Supply current
SN65LVDS32,
SN65LVDS3486
Disabled
0.25
0.5
mA
ICC
Supply current
SN65LVDS9637
No load
5.5
10
mA
II
Input current (A or B inputs)
VI = 0
-2
-10
-20
A
II
Input current (A or B inputs)
VI = 2.4 V
-1.2
-3
A
II(OFF)
Power-off input current (A or B inputs)
VCC = 0,
VI = 3.6 V
6
20
A
IIH
High-level input current (EN, G, or G inputs)
VIH = 2 V
10
A
IIL
Low-level input current (EN, G, or G inputs)
VIL = 0.8 V
10
A
IOZ
High-impedance output current
VO = 0 or VCC
10
A
All typical values are at TA = 25
C and with VCC = 3.3 V.
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going
differential input voltage threshold only.
SN65LVDSxxxx switching characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN65LVDS32
SN65LVDS3486
SN65LVDS9637
UNIT
MIN
TYP
MAX
tPLH
Propagation delay time, low-to-high-level output
1.5
2.1
3
ns
tPHL
Propagation delay time, high-to-low-level output
1.5
2.1
3
ns
tsk(p)
Pulse skew (|tPHL - tPLH|)
0
0.4
ns
tsk(o)
Channel-to-channel output skew
CL = 10 pF, See Figure 3
0.1
0.3
ns
tsk(pp)
Part-to-part skew
CL = 10 pF, See Figure 3
1
ns
tr
Output signal rise time, 20% to 80%
0.6
ns
tf
Output signal fall time, 80% to 20%
0.7
ns
tPHZ
Propagation delay time, high-level-to-high-impedance output
6.5
12
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
See Figure 4
5.5
12
ns
tPZH
Propagation delay time, high-impedance-to-high-level output
See Figure 4
8
12
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
3
12
ns
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical specified loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, same temperature, and have identical packages and test circuits.
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VID
A
B
Y
VO
VIB
VIA
VIC
(VIA + VIB)/2
Figure 2. Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED
VOLTAGES
RESULTING
DIFFERENTIAL
INPUT VOLTAGE
RESULTING
COMMON-MODE
INPUT VOLTAGE
VIA
(V)
VIB
(V)
VID
(mV)
VIC
(V)
1.25
1.15
100
1.2
1.15
1.25
-100
1.2
2.4
2.3
100
2.35
2.3
2.4
-100
2.35
0.1
0
100
0.05
0
0.1
-100
0.05
1.5
0.9
600
1.2
0.9
1.5
-600
1.2
2.4
1.8
600
2.1
1.8
2.4
-600
2.1
0.6
0
600
0.3
0
0.6
-600
0.3
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VID
VO
VIB
VIA
CL = 10 pF
tPHL
tPLH
tf
tr
80%
20%
80%
20%
VIA
VIB
VID
VO
1.4 V
1 V
0.4 V
0
-0.4 V
VOH
1.4 V
VOL
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf
1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10
0.2 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 3. Timing Test Circuit and Waveforms
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
B
A
G
G
VO
500
VTEST
10 pF
(see Note B)
1.2 V
tPZL
tPLZ
tPZL
tPLZ
tPZH
tPHZ
tPZH
tPHZ
2.5 V
1 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
2.5 V
1.4 V
VOL + 0.5 V
VOL
0
1.4 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
VOH
VOH - 0.5 V
1.4 V
0
VTEST
A
G, 1,2EN,
or 3,4EN
G
Y
VTEST
A
G
Y
Inputs
(see Note A)
1,2EN or 3,4EN
G, 1,2EN,
or 3,4EN
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf
1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500
10 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 4. Enable- and Disable-Time Test Circuit and Waveforms
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
55
45
25
15
50
100
65
75
f - Frequency - MHz
SN55LVDS32, SN65LVDS32
SUPPLY CURRENT
vs
FREQUENCY
85
150
200
35
Four Receivers, Loaded
Per Figure 3, Switching
Simultaneously
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
- Supply Current - mA
(rms)
I CC
Figure 6
2.1
1.9
1.7
1.5
-50
0
50
- Low-to-High Propagation Delay T
ime - ns
2.3
2.5
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2.7
100
TA - Free-Air Temperature -
C
t PLH(D)
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
Figure 7
2.1
1.9
1.7
1.5
-50
0
50
- High-to-Low Propagation Delay T
ime - ns
2.3
2.5
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2.7
100
t PHL(D)
TA - Free-Air Temperature -
C
VCC = 3.3 V
VCC = 3.6 V
VCC = 3 V
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 8
IOH - High-Level Output Current - mA
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-60
-50
-40
-30
-20
-10
0
V
OH
- High-Level Output V
oltage - V
Figure 9
IOL - Low-Level Output Current - mA
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
10
20
30
40
50
60
70
80
OL
V
-
Low-Level Output V
o
ltage - V
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
using an LVDS receiver with RS-422 data
Receipt of data from a TIA/EIA-422 line driver can be accomplished using a TIA/EIA-644 line receiver with the
addition of an attenuator circuit. This technique gives the user a high-speed and low-power 422 receiver.
If the ground noise between the transmitter and receiver is not a concern (less than
1 V), the answer can be
as simple as shown in Figure 10. A resistor divider circuit in front of the LVDS receiver attenuates the 422
differential signal to LVDS levels.
The resistors present a total differential load of 100
to match the characteristic impedance of the transmission
line and to reduce the signal 10:1. The maximum 422 differential output signal, or 6 V, is reduced to 600 mV.
The high input impedance of the LVDS receiver prevents input bias offsets and maintains a greater than 200-mV
differential input voltage threshold at the inputs to the divider. This circuit is used in front of each LVDS channel
that also receives 422 signals.
R1
45.3
R2
45.3
R3
5.11
R4
5.11
A
B
Y
'LVDS32
NOTE A: The components used were standard values.
R1, R2 = NRC12F45R3TR, NIC components, 45.3
, 1/8 W, 1%, 1206 package
R3, R4 = NRC12F5R11TR, NIC components, 5.11
, 1/8 W, 1%, 1206 package
The resistor values do not need to be 1% tolerance. However, it can be difficult locating a supplier of resistors having values less than
100
in stock and readily available. The user may find other suppliers with comparable parts having tolerances of 5% or even 10%.
These parts are adequate for use in this circuit.
Figure 10. RS-422 Data Input to an LVDS Receiver Under Low Ground-Noise Conditions
If ground noise between the RS-422 driver and LVDS receiver is a concern, the common-mode voltage must
be attenuated. The circuit must then be modified to connect the node between R3 and R4 to the LVDS receiver
ground. This modification to the circuit increases the common-mode voltage from
1 V to greater than
4.5 V.
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission where ground
differences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers
approach ECL speeds without the power and dual-supply requirements.
10
1
0.1
T
ransmission Distance - m
100
Signaling Rate - Mbps
TRANSMISSION DISTANCE
vs
SIGNALING RATE
10
100
1000
5% Jitter
(see Note A)
30% Jitter
(see Note A)
24 AWG UTP 96
(PVC Dielectric)
NOTE A: This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern.
Figure 11. Typical Transmission Distance Versus Signaling Rate
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
100
100
100
(see Note B)
100
3.3 V
0.1
F
(see Note A)
0.001
F
(see Note A)
VCC
See Note C
NOTES: A. Place a 0.1-
F and a 0.001-
F Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitors should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with
10%.
C. Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 12. Typical Application Circuit Schematic
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
1/4 'LVDS31
'LVDS32
500
500
20 k
20 k
3.3 V
500
500
20 k
20 k
3.3 V
7 k
7 k
10 k
3.3 k
Twisted-Pair B Only
Strb/Data_TX
Strb/Data_Enable
Data/Strobe
1 Arb_RX
2 Arb_RX
Port_Status
TpBias on
Twisted-Pair A
55
55
5 k
VG on
Twisted-Pair B
TP
TP
3.3 V
NOTES: A. Resistors are leadless, thick film (0603), 5% tolerance.
B. Decoupling capacitance is not shown but recommended.
C. VCC is 3 V to 3.6 V.
D. The differential output voltage of the 'LVDS31 can exceed that allowed by IEEE1394.
Figure 13. 100-Mbps IEEE 1394 Transceiver
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
fail-safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers in
that its output logic state can be indeterminate when the differential input voltage is between -100 mV and
100 mV if it is within its recommended input common-mode voltage range. However, TI LVDS receivers handle
the open-input circuit situation differently.
Open-input circuit means that there is little or no input current to the receiver from the data line itself. This could
be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS
receiver pulls each line of the signal pair to near V
CC
through 300-k
resistors (see Figure 14). The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high level, regardless of the differential input voltage.
Rt
300 k
300 k
VCC
VIT
2.3 V
A
B
Y
Figure 14. Open-Circuit Fail-Safe of LVDS Receiver
It is only under these conditions that the output of the receiver is valid with less than a 100-mV differential input
voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long
as it is connected as shown in Figure 14. Other termination circuits may allow a dc current to ground that could
defeat the pullup currents from the receiver and the fail-safe feature.
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
100
100
100
(see Note B)
100
VCC
See Note C
3.6 V
0.1
F
(see Note A)
1N645
(two places)
0.01
F
5 V
NOTES: A. Place a 0.1-
F Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The
capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with
10%.
C. Unused enable inputs should be tied to VCC or GND, as appropriate.
Figure 15. Operation With 5-V Supply
related information
IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at www.ti.com
for more information.
For more application guidelines, please see the following documents:
D
Low-Voltage Differential Signaling Design Notes (literature number SLLA014)
D
Interface Circuits for TIA/EIA-644 (LVDS) (literature number SLLA038)
D
Reducing EMI With LVDS (literature number SLLA030)
D
Slew Rate Control of LVDS Circuits (literature number SLLA034)
D
Using an LVDS Receiver With TIA/EIA-422 Data (literature number SLLA031)
D
Low Voltage Differential Signaling (LVDS) EVM (literature number SLLA033)
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
THERMAL PAD MECHANICAL DATA
DGN (S-PDSO-G8)
PowerPAD
t
PLASTIC SMALL-OUTLINE
NOTES:
Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and Application
Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are available at www.ti.com.
PowerPAD is a trademark of Texas Instruments
B. This drawing is subject to change without notice.
C. For additional information on the PowerPAD
package and how to take advantage of its heat dissipating abilities, refer to
PPTD041
Not to Scale
Top View
8
5
1
4
Exposed Pad
1,73 MAX
1,78 MAX
A. All linear dimensions are in millimeters.
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047 / D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0
- 8
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MECHANICAL INFORMATION
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,69
0,41
0,25
0,15 NOM
Gage Plane
4073329/B 04/98
4,98
0,25
5
3,05
4,78
2,95
8
4
3,05
2,95
1
0,38
1,07 MAX
Seating Plane
0,65
M
0,25
0
- 6
0,10
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MECHANICAL INFORMATION
DGN (S-PDSO-G8)
PowerPAD
PLASTIC SMALL-OUTLINE PACKAGE
0,69
0,41
0,25
Thermal Pad
(See Note D)
0,15 NOM
Gage Plane
4073271/A 01/98
4,98
0,25
5
3,05
4,78
2,95
8
4
3,05
2,95
1
0,38
0,15
0,05
1,07 MAX
Seating Plane
0,10
0,65
M
0,25
0
- 6
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments.
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
4040140 / D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MIN
MAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)
(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
13
14
15
16
18
17
11
10
8
9
7
5
4
3
2
0.020 (0,51)
0.010 (0,25)
6
1
28
26
27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MECHANICAL INFORMATION
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
1
20
0.290
(7,87)
0.310
0.975
(24,77)
(23,62)
0.930
(7,37)
0.245
(6,22)
(7,62)
0.300
18
16
14
PINS **
0.290
(7,87)
0.310
0.785
(19,94)
(19,18)
0.755
(7,37)
0.310
(7,87)
(7,37)
0.290
0.755
(19,18)
(19,94)
0.785
0.245
(6,22)
(7,62)
0.300
A
0.300
(7,62)
(6,22)
0.245
A MIN
A MAX
B MAX
B MIN
C MIN
C MAX
DIM
0.310
(7,87)
(7,37)
0.290
(23,10)
0.910
0.300
(7,62)
(6,22)
0.245
0
-15
Seating Plane
0.014 (0,36)
0.008 (0,20)
4040083/D 08/98
C
8
7
0.020 (0,51) MIN
B
0.070 (1,78)
0.100 (2,54)
0.065 (1,65)
0.045 (1,14)
14 PIN SHOWN
14
0.015 (0,38)
0.023 (0,58)
0.100 (2,54)
0.200 (5,08) MAX
0.130 (3,30) MIN
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22.
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
- 8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262N - JULY 1997 - REVISED MARCH 2004
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MECHANICAL INFORMATION
W (R-GDFP-F16)
CERAMIC DUAL FLATPACK
0.235 (5,97)
0.355 (9,02)
0.355 (9,02)
0.235 (5,97)
9
8
16
1
0.745 (18,92)
0.245 (6,22)
0.004 (0,10)
0.026 (0,66)
0.015 (0,38)
0.015 (0,38)
0.045 (1,14)
0.371 (9,42)
0.006 (0,15)
0.045 (1,14)
Base and Seating Plane
0.025 (0,64)
0.019 (0,48)
0.440 (11,18)
0.285 (7,24)
0.085 (2,16)
1.025 (26,04)
4040180-3 / B 03/95
0.275 (6,99)
0.305 (7,75)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL-STD-1835 GDFP1-F16 and JEDEC MO-092AC
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
5962-9762201Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
Level-NC-NC-NC
5962-9762201QEA
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
Level-NC-NC-NC
5962-9762201QFA
ACTIVE
CFP
W
16
1
TBD
A42 SNPB
Level-NC-NC-NC
5962-9762201VFA
ACTIVE
CFP
W
16
1
TBD
A42 SNPB
Level-NC-NC-NC
5962-9762202Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
Level-NC-NC-NC
SN55LVDS32W
ACTIVE
CFP
W
16
1
TBD
A42 SNPB
Level-NC-NC-NC
SN65LVDS32D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32NSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32NSRG4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32PWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3486D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3486DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DGK
ACTIVE
MSOP
DGK
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DGKG4
ACTIVE
MSOP
DGK
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DGKRG4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DGN
ACTIVE
MSOP-
Power
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DGNG4
ACTIVE
MSOP-
Power
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DGNR
ACTIVE
MSOP-
Power
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DGNRG4
ACTIVE
MSOP-
Power
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2005
Addendum-Page 1
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
no Sb/Br)
SN65LVDS9637DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ55LVDS32FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
Level-NC-NC-NC
SNJ55LVDS32J
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
Level-NC-NC-NC
SNJ55LVDS32W
ACTIVE
CFP
W
16
1
TBD
A42 SNPB
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2005
Addendum-Page 2
MECHANICAL DATA

MLCC006B OCTOBER 1996
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
4040140 / D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MIN
MAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)
(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
13
14
15
16
18
17
11
10
8
9
7
5
4
3
2
0.020 (0,51)
0.010 (0,25)
6
1
28
26
27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA

MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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amplifier.ti.com
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interface.ti.com
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www.ti.com/digitalcontrol
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logic.ti.com
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www.ti.com/military
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power.ti.com
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www.ti.com/opticalnetwork
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www.ti.com/telephony
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www.ti.com/wireless
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2005, Texas Instruments Incorporated