SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS394A SEPTEMBER 1999 REVISED DECEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Eight (`388) or Sixteen (`386) Line Receivers
Meet or Exceed the Requirements of ANSI
TIA/EIA-644 Standard
D
Integrated 110-
Line Termination
Resistors on LVDT Products
D
Designed for Signaling Rates
Up To
630 Mbps
D
SN65 Version's Bus-Terminal ESD Exceeds
15 kV
D
Operates From a Single 3.3-V Supply
D
Typical Propagation Delay Time of 2.6 ns
D
Output Skew 100 ps (Typ)
Part-To-Part Skew is Less Than 1 ns
D
LVTTL Levels are 5-V Tolerant
D
Open-Circuit Fail Safe
D
Flow-Through Pin Out
D
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
description
The `LVDS388 and `LVDT388 (
T designates
integrated termination) are eight and the
`LVDS386 and `LVDT386 sixteen differential line
receivers respectively that implement the electri-
cal characteristics of low-voltage differential
signaling (LVDS). This signaling technique lowers
the output voltage levels of 5-V differential
standard levels (such as EIA/TIA-422B) to reduce
the power, increase the switching speeds, and
allow operation with a 3-V supply rail. Any of the
eight or sixteen differential receivers will provide
a valid logical output state with a
100 mV
differential input voltage within the input common-
mode voltage range. The input common-mode
voltage range allows 1 V of ground potential
difference between two LVDS nodes. Additionally,
the high-speed switching of LVDS signals almost
always require the use of a line impedance
matching resistor at the receiving end of the cable
or transmission media. The LVDT products
eliminate this external resistor by integrating it
with the receiver.
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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GND
V
CC
V
CC
GND
ENA
A1Y
A2Y
A3Y
A4Y
ENB
B1Y
B2Y
B3Y
B4Y
GND
V
CC
V
CC
GND
C1Y
C2Y
C3Y
C4Y
ENC
D1Y
D2Y
D3Y
D4Y
END
GND
V
CC
V
CC
GND
A1A
A1B
A2A
A2B
A3A
A3B
A4A
A4B
B1A
B1B
B2A
B2B
B3A
B3B
B4A
B4B
C1A
C1B
C2A
C2B
C3A
C3B
C4A
C4B
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
GND
V
CC
ENA
A1Y
A2Y
ENB
B1Y
B2Y
GND
V
CC
GND
C1Y
C2Y
ENC
D1Y
D2Y
END
V
CC
GND
A1A
A1B
A2A
A2B
NC
B1A
B1B
B2A
B2B
NC
C1A
C1B
C2A
C2B
NC
D1A
D1B
D2A
D2B
SN65LVDS388, SN75LVDS388
SN65LVDT388, SN75LVDT388
DBT PACKAGE
(TOP VIEW)
SN65LVDS386, SN75LVDS386
SN65LVDT386, SN75LVDT386
DGG PACKAGE
(TOP VIEW)
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS394A SEPTEMBER 1999 REVISED DECEMBER 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100
. The transmission media may be printed circuit board
traces, backplanes, or cables. The large number of receivers integrated into the same substrate along with the
low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for
synchronous parallel data transfers. When used with its companion, 8- or 16-channel driver, the SN65LVDS389
or SN65LVDS387, over 300 million data transfers per second in single-edge clocked systems are possible with
very little power. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to the environment, and other system characteristics.)
Available Options
Part number
Temperature
Range
Number of
Receivers
Bus-Pin ESD
SN65LVDS386DGG
40
_
C to 85
_
C
16
15 kV
SN65LVDT386DGG
40
_
C to 85
_
C
16
15 kV
SN75LVDS386DGG
0
_
C to 70
_
C
16
4 kV
SN75LVDT386DGG
0
_
C to 70
_
C
16
4 kV
SN65LVDS388DBT
40
_
C to 85
_
C
8
15 kV
SN65LVDT388DBT
40
_
C to 85
_
C
8
15 kV
SN75LVDS388DBT
0
_
C to 70
_
C
8
4 kV
SN75LVDT388DBT
0
_
C to 70
_
C
8
4 kV
logic diagram (positive logic)
'LVDx386
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
'LVDT386 ONLY
'LVDx388
EN
1A
1B
2A
2B
1Y
2Y
'LVDT388 ONLY
EN
Function Table
SNx5LVD386/388 and SNx5LVDT386/388
DIFFERENTIAL INPUT
ENABLES
OUTPUT
A-B
EN
Y
VID
100 mV
H
H
-100 mV < VID
100 mV
H
?
VID
-100 mV
H
L
X
L
Z
Open
H
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS394A SEPTEMBER 1999 REVISED DECEMBER 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
equivalent input and output schematic diagrams
300 k
300 k
VCC
7 V
7 V
A Input
B Input
7 V
100
VCC
EN
VCC
5
7 V
Y Output
300 k
110
'LVDT Devices Only
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
CC
(see Note 1)
0.5 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range:
Enables or Y
0.5 V to V
CC
+ 2 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A or B
0.5 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: (see Note 2)
SN65' (A, B, and GND)
Class 3, A:15 kV, B: 700 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN65' (All pins)
Class 3, A: 8 kV, B:600 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN75' (A, B, and GND)
Class 2, A:4 kV, B: 400 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN75' (All pins)
Class 2, A: 2 kV, B:200 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation
See Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA
25
C
DERATING FACTOR
ABOVE TA = 25
C
TA = 70
C
POWER RATING
TA = 85
C
POWER RATING
DBT
1071 mW
8.5 mW/
C
688 mW
556 mW
DGG
2094 mW
16.7 mW/
C
1342 mW
1089 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.
SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS394A SEPTEMBER 1999 REVISED DECEMBER 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
3
3.3
3.6
V
High-level input voltage, VIH
2
V
Low-level input voltage, VIL
0.8
V
Magnitude of differential input voltage,
VID
0.1
0.6
V
Commonmode input voltage, VIC (see Figure 4)
|V
ID
|
2
2.4
*
|V
ID
|
2
V
VCC 0.8
Operating free-air temperature TA
SN75'
0
70
C
O erating free-air tem erature, TA
SN65'
40
85
C
SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS394A SEPTEMBER 1999 REVISED DECEMBER 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VITH+
Positivegoing differential input voltage threshold
See Figure 1 and Table 1
100
mV
VITH
Negativegoing differential input voltage threshold
See Figure 1 and Table 1
100
mV
VOH
Highlevel output voltage
IOH = 8 mA
2.4
3
V
VOL
Lowlevel output voltage
IOL = 8 mA
0.2
0.4
V
ICC
Supply current
Enabled, No
load
50
70
mA
ICC
Supply current
Disabled
3
mA
'LVDS
VI = 0 V
13
20
II
Input current (A or B inputs)
'LVDS
VI = 2.4 V
1.2
3
A
II
Input current (A or B inputs)
'LVDT
VI = 0 V, other input open
40
A
'LVDT
VI = 2.4 V, other input open
2.4
IID
Differential input current |IIA IIB|
`LVDS
VIA= 0 V,
VIB = 0.1V,
VIA= 2.4 V,
VIB = 2.3 V
2
A
IID
Differential input current (IIA IIB)
`LVDT
VIA= 0.2 V,
VIB = 0V,
VIA= 2.4 V,
VIB = 2.2 V
1.5
2.2
mA
II(OFF)
Poweroff Input current (A or B inputs)
`LVDS
VCC = 0 V,
VI=2.4 V
12
20
A
II(OFF)
Poweroff Input current (A or B inputs)
`LVDT
VCC = 0 V,
VI=2.4 V
40
A
IIH
Highlevel input current (enables)
VIH = 2 V
10
A
IIL
Lowlevel input current (enables)
VIL = 0.8 V
10
A
IOZ
High impedance output current
VO = 0 V
1
A
IOZ
Highimpedance output current
VO = 3.6 V
10
A
CIN
Input Capacitance, A or B input to GND
VID = 0.4 sin 2.5E09 t V
5
pF
Z(t)
Termination impedance
VID = 0.4 sin 2.5E09 t V
88
132
All typical values are at 25
C and with a 3.3 V supply.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
1
2.6
4
ns
tPHL
Propagation delay time, high-to-low-level output
1
2.5
4
ns
tr
Differential output signal rise time
500
800
1200
ps
tf
Differential output signal fall time
See Figure 2
500
800
1200
ps
tsk(p)
Pulse skew (|tPHL tPLH|)
g
150
600
ps
tsk(o)
Output skew
100
400
ps
tsk(pp)
Part-to-part skew
1
ns
tPZH
Propagation delay time, high-impedance-to-high-level output
7
15
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
See Figure 3
7
15
ns
tPHZ
Propagation delay time, high-level-to-high-impedance output
See Figure 3
7
15
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
7
15
ns
All typical values are at 25
C and with a 3.3 V supply.
tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected together.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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