SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D SEPTEMBER 1999 REVISED MAY 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Four ('391), Eight ('389) or Sixteen ('387)
Line Drivers Meet or Exceed the
Requirements of ANSI EIA / TIA-644
Standard
D
Designed for Signaling Rates
up to
630 Mbps With Very Low Radiation (EMI)
D
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100-
Load
D
Propagation Delay Times Less Than 2.9 ns
D
Output Skew Is Less Than 150 ps
D
Part-to-Part Skew Is Less Than 1.5 ns
D
35-mW Total Power Dissipation in Each
Driver Operating at 200 MHz
D
Driver Is High Impedance When Disabled or
With V
CC
< 1.5 V
D
SN65' Version Bus-Pin ESD Protection
Exceeds 15 kV
D
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
D
Low-Voltage TTL (LVTTL) Logic Inputs Are
5-V Tolerant
description
This family of four, eight, and sixteen differential
line drivers implements the electrical characteris-
tics of low-voltage differential signaling (LVDS).
This signaling technique lowers the output voltage
levels of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a
3.3-V supply rail. Any of the sixteen current-mode
drivers will deliver a minimum differential output
voltage magnitude of 247 mV into a 100-
load
when enabled.
The intended application of this device and signaling technique is for point-to-point and multidrop baseband data
transmission over controlled impedance media of approximately 100
. The transmission media can be
printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same
substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of
clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel
receivers, the SN65LVDS386 or SN65LVDS388, over 300 million data transfers per second in single-edge
clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)
Copyright
2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
V
CC
V
CC
GND
ENA
A1A
A2A
A3A
A4A
ENB
B1A
B2A
B3A
B4A
GND
V
CC
V
CC
GND
C1A
C2A
C3A
C4A
ENC
D1A
D2A
D3A
D4A
END
GND
V
CC
V
CC
GND
A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
C1Y
C1Z
C2Y
C2Z
C3Y
C3Z
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
D3Z
D4Y
D4Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
GND
V
CC
GND
ENA
A1A
A2A
A3A
A4A
GND
V
CC
GND
B1A
B2A
B3A
B4A
ENB
GND
V
CC
GND
A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
NC
NC
NC
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
'LVDS389
DBT PACKAGE
(TOP VIEW)
'LVDS387
DGG PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN1,2
1A
2A
V
CC
GND
3A
4A
EN3,4
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
'LVDS391
D OR PW PACKAGE
(TOP VIEW)
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D SEPTEMBER 1999 REVISED MAY 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
When disabled, the driver outputs are high impedance. Each driver input (A) and enable (EN) have an internal
pulldown that will drive the input to a low level when open circuited.
The SN65LVDS387, SN65LVDS389, and SN65LVDS391 are characterized for operation from 40
C to 85
C.
The SN75LVDS387, SN75LVDS389, and SN75LVDS391 are characterized for operation from 0
C to 70
C.
logic diagram (positive logic)
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
4A
3A
2A
1A
(1/4 of 'LVDS387 or 1/2 of 'LVDS389 shown)
EN
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
4A
3A
2A
1A
('LVDS391 shown)
EN
EN
AVAILABLE OPTIONS
PART NUMBER
TEMPERATURE
RANGE
NO. OF
DRIVERS
BUS-PIN
ESD
SN65LVDS387DGG
40
C to 85
C
16
15 kV
SN75LVDS387DGG
0
C to 70
C
16
4 kV
SN65LVDS389DBT
40
C to 85
C
8
15 kV
SN75LVDS389DBT
0
C to 70
C
8
4 kV
SN65LVDS391D
40
C to 85
C
4
15 kV
SN75LVDS391D
0
C to 70
C
4
4 kV
SN65LVDS391PW
40
C to 85
C
4
15 kV
SN75LVDS391PW
0
C to 70
C
4
4 kV
This package is available taped and reeled. To order this packaging option, add
an R suffix to the part number (e.g., SN65LVDS387DGGR).
DRIVER FUNCTION TABLE
INPUT
ENABLE
OUTPUTS
A
EN
Y
Z
H
H
H
L
L
H
L
H
X
L
Z
Z
OPEN
H
L
H
H = high-level, L = low-level, X = irrelevant,
Z = high-impedance (off)
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D SEPTEMBER 1999 REVISED MAY 2001
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
equivalent input and output schematic diagrams
7 V
300 k
50
VCC
A or EN
Input
VCC
5
7 V
Y or Z
Output
EQUIVALENT OF EACH A OR EN INPUT
TYPICAL OF ALL OUTPUTS
10 k
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range: Inputs
0.5 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Y or Z
0.5 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: SN65' (Y, Z, and GND)
Class 3, A:15 kV, B: 500 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN75' (Y, Z, and GND)
Class 3, A:4 kV, B: 400 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation
(see Dissipation Rating Table)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA
25
C
DERATING FACTOR
ABOVE TA = 25
C
TA = 70
C
POWER RATING
TA = 85
C
POWER RATING
D
950 mW
7.6 mW/
C
608 mW
494 mW
DBT
1071 mW
8.5 mW/
C
688 mW
556 mW
DGG
2094 mW
16.7 mW/
C
1342 mW
1089 mW
PW
774 mW
6.2 mW/
C
496 mW
402 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
3
3.3
3.6
V
High-level input voltage, VIH
2
V
Low-level input voltage, VIL
0.8
V
Operating free-air temperature TA
SN75'
0
70
C
O erating free-air tem erature, TA
SN65'
40
85
C
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D SEPTEMBER 1999 REVISED MAY 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
|VOD|
Differential output voltage magnitude
RL = 100
247
340
454
|VOD|
Change in differential output voltage
magnitude between logic states
RL = 100
, ,
See Figure 1 and Figure 2
50
50
mV
VOC(SS)
Steady-state common-mode output voltage
1.125
1.375
V
VOC(SS)
Change in steady-state common-mode output
voltage between logic states
See Figure 3
50
50
mV
VOC(PP)
Peak-to-peak common-mode output voltage
50
150
mV
'LVDS387
Enabled,
85
95
'LVDS389
Enabled,
RL = 100
,
50
70
ICC
Supply current
'LVDS391
VIN = 0.8 V or 2 V
20
26
mA
ICC
Supply current
'LVDS387
Di
bl d
0.5
1.5
mA
'LVDS389
Disabled,
VIN = 0 V or VCC
0.5
1.5
'LVDS391
VIN = 0 V or VCC
0.5
1.3
IIH
High-level input current
VIH = 2 V
3
20
A
IIL
Low-level input current
VIL = 0.8 V
2
10
A
IOS
Short circuit output current
VOY or VOZ = 0 V
24
mA
IOS
Short-circuit output current
VOD = 0 V
12
mA
IOZ
High-impedance output current
VO = 0 V or VCC
1
A
IO(OFF)
Power-off output current
VCC = 1.5 V,
VO = 2.4 V
1
A
CIN
Input capacitance
VI = 0.4 sin (4E6
t) + 0.5 V
5
pF
CO
Output capacitance
VI = 0.4 sin (4E6
t) + 0.5 V,
Disabled
9.4
pF
All typical values are at 25
C and with a 3.3-V supply.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
0.9
1.7
2.9
ns
tPHL
Propagation delay time, high-to-low-level output
0.9
1.6
2.9
ns
tr
Differential output signal rise time
RL = 100
0.4
0.8
1
ns
tf
Differential output signal fall time
RL = 100
,
CL = 10 pF,
0.4
0.8
1
ns
tsk(p)
Pulse skew (|tPHL tPLH|)
L
See Figure 4
150
500
ps
tsk(o)
Output skew
80
150
ps
tsk(pp)
Part-to-part skew
1.5
ns
tPZH
Propagation delay time, high-impedance-to-high-level output
6.4
15
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
See Figure 5
5.9
15
ns
tPHZ
Propagation delay time, high-level-to-high-impedance output
See Figure 5
3.5
15
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
4.5
15
ns
All typical values are at 25
C and with a 3.3-V supply.
tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected together.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in this data
sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits.
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D SEPTEMBER 1999 REVISED MAY 2001
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
GND
VI
A
(VOY + VOZ)/2
IOZ
IOY
Y
Z
VOD
VOY
VOC
II
VOZ
Figure 1. Voltage and Current Definitions
3.75 k
0 V
VTEST
2.4 V
Y
Z
VOD
Input
100
3.75 k
Figure 2. VOD Test Circuit
Y
Z
Input
50 pF
49.9
1% (2 Places)
VOC
VO
VOC(PP)
VOC(SS)
0 V
3 V
VI
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf
1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500
10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP)
is made on test equipment with a 3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Y
Z
VOD
Input
CL = 10 pF
(2 Places)
100
1 %
2 V
1.4 V
0.8 V
tPLH
tPHL
100%
80%
20%
0%
Input
Output
0 V
tf
tr
VOD(H)
VOD(L)
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf
1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse
width = 10
0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
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