SN54ABT574, SN74ABT574A
OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
SCBS191F - JANUARY 1991 - REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Typical V
OLP
(Output Ground Bounce)
<1 V at V
CC
= 5 V, T
A
= 25
C
D
High-Drive Outputs (-32-mA I
OH
, 64-mA I
OL
)
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD 17
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
SN54ABT574 . . . J OR W PACKAGE
SN74ABT574A . . . DB, DW, N, NS,
OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
SN54ABT574 . . . FK PACKAGE
(TOP VIEW)
2D
1D
OE
8Q
7Q
1Q
8D
GND
CLK
V
CC
SN74ABT574A . . . RGY PACKAGE
(TOP VIEW)
1
20
10
11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
6D
7D
8D
CLK
V
G
ND
CC
OE
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP - N
Tube
SN74ABT574AN
SN74ABT574AN
QFN - RGY
Tape and reel
SN74ABT574ARGYR
AB574A
SOIC - DW
Tube
SN74ABT574ADW
ABT574A
SOIC - DW
Tape and reel
SN74ABT574ADWR
ABT574A
-40
C to 85
C
SOP - NS
Tape and reel
SN74ABT574ANSR
ABT574A
-40
C to 85
C
SSOP - DB
Tape and reel
SN74ABT574ADBR
AB574A
TSSOP - PW
Tube
SN74ABT574APW
AB574A
TSSOP - PW
Tape and reel
SN74ABT574APWR
AB574A
VFBGA - GQN
Tape and reel
SN74ABT574AGQNR
AB574A
VFBGA - ZQN (Pb-free)
Tape and reel
SN74ABT574AZQNR
AB574A
CDIP - J
Tube
SNJ54ABT574J
SNJ54ABT574J
-55
C to 125
C
CFP - W
Tube
SNJ54ABT574W
SNJ54ABT574W
-55 C to 125 C
LCCC - FK
Tube
SNJ54ABT574FK
SNJ54ABT574FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ABT574, SN74ABT574A
OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
SCBS191F - JANUARY 1991 - REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The eight flip-flops of the SN54ABT574 and SN74ABT574A are edge-triggered D-type flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
terminal assignments
1
2
3
4
A
1D
OE
VCC
1Q
B
3D
3Q
2D
2Q
C
5D
4D
5Q
4Q
D
7D
7Q
6D
6Q
E
GND
8D
CLK
8Q
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE
CLK
D
OUTPUT
Q
L
H
H
L
L
L
L
H or L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
CLK
1D
1Q
To Seven Other Channels
C1
1
11
2
19
1D
Pin numbers shown are for the DB, DW, FK, J, N, NS, PW, RGY, and W packages.
SN74ABT574A . . . GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
4
A
B
C
D
E
SN54ABT574, SN74ABT574A
OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
SCBS191F - JANUARY 1991 - REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
O
-0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54ABT574 96
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT574A 128
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-18 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): GQN/ZQN package
78
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): N package
69
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): NS package
60
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package
83
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package
37
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
SN54ABT574
SN74ABT574A
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
IOH
High-level output current
-24
-32
mA
IOL
Low-level output current
48
64
mA
t/
v
Input transition rise or fall rate
Outputs enabled
5
5
ns/V
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54ABT574, SN74ABT574A
OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
SCBS191F - JANUARY 1991 - REVISED SEPTEMBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25
C
SN54ABT574
SN74ABT574A
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VIK
VCC = 4.5 V,
II = -18 mA
-1.2
-1.2
-1.2
V
VCC = 4.5 V,
IOH = -3 mA
2.5
2.5
2.5
VOH
VCC = 5 V,
IOH = -3 mA
3
3
3
V
VOH
VCC = 4.5 V
IOH = -24 mA
2
2
V
VCC = 4.5 V
IOH = -32 mA
2*
2
VOL
VCC = 4.5 V
IOL = 48 mA
0.55
0.55
V
VOL
VCC = 4.5 V
IOL = 64 mA
0.55*
0.55
V
Vhys
100
mV
II
VCC = 5.5 V,
VI = VCC or GND
1
1
1
A
IOZH
VCC = 5.5 V,
VO = 2.7 V
10
10
10
A
IOZL
VCC = 5.5 V,
VO = 0.5 V
-10
-10
-10
A
Ioff
VCC = 0,
VI or VO
4.5 V
100
500
100
A
ICEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high
50
50
50
A
IO
VCC = 5.5 V,
VO = 2.5 V
-50
-100
-180
-50
-180
-50
-180
mA
VCC = 5.5 V, IO = 0,
Outputs high
1
250
250
250
A
ICC
VCC = 5.5 V, IO = 0,
VI = VCC or GND
Outputs low
24
30
30
30
mA
ICC
VI = VCC or GND
Outputs disabled
0.5
250
250
250
A
ICC
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
1.5
1.5
1.5
mA
Ci
VI = 2.5 V or 0.5 V
3.5
pF
Co
VO = 2.5 V or 0.5 V
6.5
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
All typical values are at VCC = 5 V.
This data-sheet limit may vary among suppliers.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT574
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
fclock
Clock frequency
150
150
MHz
tw
Pulse duration, CLK high or low
3.3
3.3
ns
tsu
Setup time, data before CLK
High
1.5
1.5
ns
tsu
Setup time, data before CLK
Low
2
2
ns
th
Hold time, data after CLK
High or low
2
2
ns
SN54ABT574, SN74ABT574A
OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
SCBS191F - JANUARY 1991 - REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN74ABT574A
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
fclock
Clock frequency
150
150
MHz
tw
Pulse duration, CLK high or low
3.3
3.3
ns
tsu
Setup time, data before CLK
High
1
1
ns
tsu
Setup time, data before CLK
Low
1.5
1.5
ns
th
Hold time, data after CLK
High or low
1.8
1.8
ns
This data-sheet limit may vary among suppliers.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
SN54ABT574
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
fmax
150
200
150
MHz
tPLH
CLK
Q
2.2
3.9
6.2
2.2
7
ns
tPHL
CLK
Q
3
4.8
7
3
7.4
ns
tPZH
OE
Q
1
3.3
5
1
5.8
ns
tPZL
OE
Q
2.5
4.7
5.9
2.5
7.2
ns
tPHZ
OE
Q
2.4
4.9
6.2
2.4
7.2
ns
tPLZ
OE
Q
2
4
5.8
2
6.9
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
SN74ABT574A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
fmax
150
200
150
MHz
tPLH
CLK
Q
2.2
3.9
6.2
2.2
6.8
ns
tPHL
CLK
Q
3
4.8
6.6
3
7.1
ns
tPZH
OE
Q
1
3.3
4.3
1
5.1
ns
tPZL
OE
Q
2.1
4.7
5.9
2.1
6.7
ns
tPHZ
OE
Q
2.4
4.9
6.2
2.4
7
ns
tPLZ
OE
Q
2
4
5.8
2
6.5
ns
This data-sheet limit may vary among suppliers.
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