SN54AC373, SN74AC373
OCTAL D TYPE TRANSPARENT LATCHES
WITH 3 STATE OUTPUTS
SCAS540D - OCTOBER 1995 - REVISED OCTOBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
2-V to 6-V V
CC
Operation
D
Inputs Accept Voltages to 6 V
D
Max t
pd
of 9.5 ns at 5 V
D
3-State Noninverting Outputs Drive Bus
Lines Directly
D
Full Parallel Access for Loading
description/ordering information
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in bus-organized systems without need for
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP - N
Tube
SN74AC373N
SN74AC373N
SOIC - DW
Tube
SN74AC373DW
AC373
SOIC - DW
Tape and reel
SN74AC373DWR
AC373
-40
C to 85
C
SOP - NS
Tape and reel
SN74AC373NSR
AC373
-40 C to 85 C
SSOP - DB
Tape and reel
SN74AC373DBR
AC373
TSSOP - PW
Tube
SN74AC373PW
AC373
TSSOP - PW
Tape and reel
SN74AC373PWR
AC373
CDIP - J
Tube
SNJ54AC373J
SNJ54AC373J
-55
C to 125
C
CFP - W
Tube
SNJ54AC373W
SNJ54AC373W
-55 C to 125 C
LCCC - FK
Tube
SNJ54AC373FK
SNJ54AC373FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D
1Q
OE
5Q
5D
8Q
4Q
G
ND
LE
V
CC
SN54AC373 . . . FK PACKAGE
(TOP VIEW)
SN54AC373 . . . J OR W PACKAGE
SN74AC373 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54AC373, SN74AC373
OCTAL D TYPE TRANSPARENT LATCHES
WITH 3 STATE OUTPUTS
SCAS540D - OCTOBER 1995 - REVISED OCTOBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
LE
1D
1Q
1
11
3
2
To Seven Other Channels
C1
1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
69
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
60
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
83
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54AC373, SN74AC373
OCTAL D TYPE TRANSPARENT LATCHES
WITH 3 STATE OUTPUTS
SCAS540D - OCTOBER 1995 - REVISED OCTOBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54AC373
SN74AC373
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2
6
2
6
V
VCC = 3 V
2.1
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VIH
High-level input voltage
VCC = 5.5 V
3.85
3.85
V
VCC = 3 V
0.9
0.9
VIL
Low-level input voltage
VCC = 4.5V
1.35
1.35
V
VIL
Low-level input voltage
VCC = 5.5 V
1.65
1.65
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 3 V
-12
-12
IOH
High-level output current
VCC = 4.5 V
-24
-24
mA
IOH
High-level output current
VCC = 5.5 V
-24
-24
mA
VCC = 3 V
12
12
IOL
Low-level output current
VCC = 4.5 V
24
24
mA
IOL
Low-level output current
VCC = 5.5 V
24
24
mA
t/
v
Input transition rise or fall rate
8
8
ns/V
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54AC373
SN74AC373
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
2.9
IOH = -50
A
4.5 V
4.4
4.4
4.4
VOH
IOH = -50
A
5.5 V
5.4
5.4
5.4
V
VOH
IOH = -12 mA
3 V
2.56
2.4
2.46
V
IOH = -24 mA
4.5 V
3.86
3.7
3.76
IOH = -24 mA
5.5 V
4.86
4.7
4.76
3 V
0.1
0.1
0.1
IOL = 50
A
4.5 V
0.1
0.1
0.1
VOL
IOL = 50
A
5.5 V
0.1
0.1
0.1
V
VOL
IOL = 12 mA
3 V
0.36
0.5
0.44
V
IOL = 24 mA
4.5 V
0.36
0.5
0.44
IOL = 24 mA
5.5 V
0.36
0.5
0.44
II
VI = VCC or GND
5.5 V
0.1
1
1
A
IOZ
VO = VCC or GND
5.5 V
0.25
5
2.5
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
4
80
40
A
Ci
VI = VCC or GND
5 V
4.5
pF
SN54AC373, SN74AC373
OCTAL D TYPE TRANSPARENT LATCHES
WITH 3 STATE OUTPUTS
SCAS540D - OCTOBER 1995 - REVISED OCTOBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
SN54AC373
SN74AC373
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration, LE high
5.5
6.5
6
ns
tsu
Setup time, data before LE
5.5
6.5
6
ns
th
Hold time, data after LE
1
1
1
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
SN54AC373
SN74AC373
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration, LE high
4
5
4.5
ns
tsu
Setup time, data before LE
4
5
4.5
ns
th
Hold time, data after LE
1
1
1
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
TO
TO
TA = 25
C
SN54AC373
SN74AC373
UNIT
PARAMETER
TO
(INPUT)
TO
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
D
Q
1.5
10
13.5
1
16.5
1.5
15
ns
tPHL
D
Q
1.5
9.5
13.0
1
16
1.5
14.5
ns
tPLH
LE
Q
1.5
10
13.5
1
16.5
1.5
15
ns
tPHL
LE
Q
1.5
9.5
12.5
1
15
1.5
14
ns
tPZH
OE
Q
1.5
9
11.5
1
14
1
13
ns
tPZL
OE
Q
1.5
8.5
11.5
1
13.5
1
13
ns
tPHZ
OE
Q
1.5
10
12.5
1
16
1
14.5
ns
tPLZ
OE
Q
1.5
8
11.5
1
13
1
12.5
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
TO
TO
TA = 25
C
SN54AC373
SN74AC373
UNIT
PARAMETER
TO
(INPUT)
TO
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
D
Q
1.5
7
9.5
1
11.5
1.5
10.5
ns
tPHL
D
Q
1.5
7
9.5
1
11.5
1.5
10.5
ns
tPLH
LE
Q
1.5
7.5
9.5
1
12
1.5
10.5
ns
tPHL
LE
Q
1.5
7
9.5
1
11
1.5
10.5
ns
tPZH
OE
Q
1.5
7
8.5
1
10.5
1
9.5
ns
tPZL
OE
Q
1.5
6.5
8.5
1
10
1
9.5
ns
tPHZ
OE
Q
1.5
8
11
1
13.5
1
12.5
ns
tPLZ
OE
Q
1.5
6.5
8.5
1
10.5
1
10
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 1 MHz
40
pF
SN54AC373, SN74AC373
OCTAL D TYPE TRANSPARENT LATCHES
WITH 3 STATE OUTPUTS
SCAS540D - OCTOBER 1995 - REVISED OCTOBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
50% VCC
50% VCC
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
50%VCC
VOL + 0.3 V
50% VCC
0 V
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
Open
TEST
S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
Input
50% VCC
50% VCC
VOH - 0.3 V
50% VCC
50% VCC
50% VCC
50% VCC
VCC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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