SN74AHC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCLS379D AUGUST 1997 REVISED JANUARY 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
EPIC
TM
(Enhanced-Performance Implanted
CMOS) Process
D
Operating Range 2-V to 5.5-V V
CC
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline Transistor (DBV, DCK)
Packages
description
The SN74AHC1G126 is a single bus buffer gate/line driver with 3-state output. The output is disabled when the
output-enable (OE) input is low. When OE is high, true data is passed from the A input to the Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
The SN74AHC1G126 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
INPUTS
OUTPUT
OE
A
Y
H
H
H
H
L
L
L
X
Z
logic symbol
EN
1
OE
2
A
Y
4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
A
Y
OE
1
2
4
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
5
4
OE
A
GND
V
CC
Y
SN74AHC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCLS379D AUGUST 1997 REVISED JANUARY 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DBV package
347
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package
389
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
VCC
Supply voltage
2
5.5
V
VCC = 2 V
1.5
VIH
High-level input voltage
VCC = 3 V
2.1
V
VCC = 5.5 V
3.85
VCC = 2 V
0.5
VIL
Low-level input voltage
VCC = 3 V
0.9
V
VCC = 5.5 V
1.65
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 2 V
50
m
A
IOH
High-level output current
VCC = 3.3 V
0.3 V
4
mA
VCC = 5 V
0.5 V
8
mA
VCC = 2 V
50
m
A
IOL
Low-level output current
VCC = 3.3 V
0.3 V
4
mA
VCC = 5 V
0.5 V
8
mA
t/
v
Input transition rise or fall rate
VCC = 3.3 V
0.3 V
100
ns/V
t/
v
Input transition rise or fall rate
VCC = 5 V
0.5 V
20
ns/V
TA
Operating free-air temperature
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74AHC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCLS379D AUGUST 1997 REVISED JANUARY 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
2 V
1.9
2
1.9
IOH = 50
m
A
3 V
2.9
3
2.9
VOH
4.5 V
4.4
4.5
4.4
V
IOH = 4 mA
3 V
2.58
2.48
IOH = 8 mA
4.5 V
3.94
3.8
2 V
0.1
0.1
IOL = 50
m
A
3 V
0.1
0.1
VOL
4.5 V
0.1
0.1
V
IOL = 4 mA
3 V
0.36
0.44
IOL = 8 mA
4.5 V
0.36
0.44
II
VI = VCC or GND
0 V to 5.5 V
0.1
1
m
A
IOZ
VI = VCC or GND
5.5 V
0.25
2.5
m
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
1
10
m
A
Ci
VI = VCC or GND
5 V
4
10
10
pF
Co
VO = VCC or GND
5 V
10
pF
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
A
Y
CL = 15 pF
5.6
8
1
9.5
ns
tPHL
A
Y
CL = 15 pF
5.6
8
1
9.5
ns
tPZH
OE
Y
CL = 15 pF
5.4
8
1
9.5
ns
tPZL
OE
Y
CL = 15 pF
5.4
8
1
9.5
ns
tPHZ
OE
Y
CL = 15 pF
7
9.7
1
11.5
ns
tPLZ
OE
Y
CL = 15 pF
7
9.7
1
11.5
ns
tPLH
A
Y
CL = 50 pF
8.1
11.5
1
13
ns
tPHL
A
Y
CL = 50 pF
8.1
11.5
1
13
ns
tPZH
OE
Y
CL = 50 pF
7.9
11.5
1
13
ns
tPZL
OE
Y
CL = 50 pF
7.9
11.5
1
13
ns
tPHZ
OE
Y
CL = 50 pF
9.5
13.2
1
15
ns
tPLZ
OE
Y
CL = 50 pF
9.5
13.2
1
15
ns
SN74AHC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCLS379D AUGUST 1997 REVISED JANUARY 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
A
Y
CL = 15 pF
3.8
5.5
1
6.5
ns
tPHL
A
Y
CL = 15 pF
3.8
5.5
1
6.5
ns
tPZH
OE
Y
CL = 15 pF
3.6
5.1
1
6
ns
tPZL
OE
Y
CL = 15 pF
3.6
5.1
1
6
ns
tPHZ
OE
Y
CL = 15 pF
4.6
6.8
1
8
ns
tPLZ
OE
Y
CL = 15 pF
4.6
6.8
1
8
ns
tPLH
A
Y
CL = 50 pF
5.3
7.5
1
8.5
ns
tPHL
A
Y
CL = 50 pF
5.3
7.5
1
8.5
ns
tPZH
OE
Y
CL = 50 pF
5.1
7.1
1
8
ns
tPZL
OE
Y
CL = 50 pF
5.1
7.1
1
8
ns
tPHZ
OE
Y
CL = 50 pF
6.1
8.8
1
10
ns
tPLZ
OE
Y
CL = 50 pF
6.1
8.8
1
10
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load,
f = 1 MHz
14
pF
SN74AHC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCLS379D AUGUST 1997 REVISED JANUARY 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
50% VCC
VOL
+ 0.3 V
50% VCC
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST
S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr
3 ns, tf
3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL = 1 k
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
VOH
0.3 V
Figure 1. Load Circuit and Voltage Waveforms
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