SN54AHC273, SN74AHC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS376G JUNE 1997 REVISED JULY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Operating Range 2-V to 5.5-V V
CC
D
Contain Eight Flip-Flops With Single-Rail
Outputs
D
Direct Clear Input
D
Individual Data Input to Each Flip-Flop
D
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
1000-V Charged-Device Model (C101)
description/ordering information
These circuits are positive-edge-triggered D-type
flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going pulse.
When CLK is at either the high or low level, the
D input has no effect at the output.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74AHC273N
SN74AHC273N
SOIC
DW
Tube
SN74AHC273DW
AHC273
SOIC DW
Tape and reel
SN74AHC273DWR
AHC273
40
C to 85
C
SOP NS
Tape and reel
SN74AHC273NSR
AHC273
40
C to 85
C
SSOP DB
Tape and reel
SN74AHC273DBR
HA273
TSSOP
PW
Tube
SN74AHC273PW
HA273
TSSOP PW
Tape and reel
SN74AHC273PWR
HA273
TVSOP DGV
Tape and reel
SN74AHC273DGVR
HA273
CDIP J
Tube
SNJ54AHC273J
SNJ54AHC273J
55
C to 125
C
CFP W
Tube
SNJ54AHC273W
SNJ54AHC273W
LCCC FK
Tube
SNJ54AHC273FK
SNJ54AHC273FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54AHC273 . . . J OR W PACKAGE
SN74AHC273 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54AHC273 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
2Q
3Q
3D
4D
1D
1Q
CLR
5Q
5D
8Q
4Q
GND
CLK
V
CC
8D
7D
7Q
6Q
6D
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54AHC273, SN74AHC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS376G JUNE 1997 REVISED JULY 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
CLR
CLK
D
OUTPUT
Q
L
X
X
L
H
H
H
H
L
L
H
L
X
Q0
logic diagram (positive logic)
CLK
1D
1Q
2D
2Q
3D
3Q
4D
4Q
5D
5Q
6D
6Q
7D
7Q
8D
8Q
CLR
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
3
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
11
1
logic diagram, each flip-flop (positive logic)
CLK(I)
R
Q
C
C
D
C
C
C
C
C
C
TG
C
C
TG
TG
TG
SN54AHC273, SN74AHC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS376G JUNE 1997 REVISED JULY 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
75 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
92
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
69
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
60
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
83
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AHC273
SN74AHC273
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2
5.5
2
5.5
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 3 V
2.1
2.1
V
VCC = 5.5 V
3.85
3.85
VCC = 2 V
0.5
0.5
VIL
Low-level input voltage
VCC = 3 V
0.9
0.9
V
VCC = 5.5 V
1.65
1.65
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
50
50
m
A
IOH
High-level output current
VCC = 3.3 V
0.3 V
4
4
mA
VCC = 5 V
0.5 V
8
8
mA
VCC = 2 V
50
50
m
A
IOL
Low-level output current
VCC = 3.3 V
0.3 V
4
4
mA
VCC = 5 V
0.5 V
8
8
mA
t/
v
Input transition rise or fall rate
VCC = 3.3 V
0.3 V
100
100
ns/V
t/
v
Input transition rise or fall rate
VCC = 5 V
0.5 V
20
20
ns/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54AHC273, SN74AHC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS376G JUNE 1997 REVISED JULY 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54AHC273
SN74AHC273
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
1.9
1.9
1.9
IOH = 50
m
A
3 V
2.9
2.9
2.9
VOH
4.5 V
4.4
4.4
4.4
V
IOH = 4 mA
3 V
2.58
2.48
2.48
IOH = 8 mA
4.5 V
3.94
3.8
3.8
2 V
0.1
0.1
0.1
IOL = 50
m
A
3 V
0.1
0.1
0.1
VOL
4.5 V
0.1
0.1
0.1
V
IOL = 4 mA
3 V
0.36
0.5
0.44
IOL = 8 mA
4.5 V
0.36
0.5
0.44
II
VI = 5.5 V or GND
0 V to 5.5 V
0.1
1*
1
m
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
4
40
40
m
A
Ci
VI = VCC or GND
5 V
2.5
10
10
pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
0.3 V
(unless otherwise noted) (see Figure 1)
SN54AHC273
SN74AHC273
TA = 25
C
MIN
MAX
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
Pulse duration
CLR low
5
6
5
6
ns
tw
Pulse duration
CLK high or low
5
6.5
5
6.5
ns
t
Setup time
Data before CLK
5.5
6.5
5.5
6.5
ns
tsu
Setup time
CLR before CLK
2.5
2.5
2.5
2.5
ns
th
Hold time, data after CLK
1.5
2
1
1
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
SN54AHC273
SN74AHC273
TA = 25
C
MIN
MAX
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
Pulse duration
CLR low
5
5
5
5
ns
tw
Pulse duration
CLK high or low
5
5
5
5
ns
t
Setup time
Data before CLK
4.5
4.5
4.5
4.5
ns
tsu
Setup time
CLR before CLK
2
2
2
2
ns
th
Hold time, data after CLK
1.5
2
1
1
ns
SN54AHC273, SN74AHC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS376G JUNE 1997 REVISED JULY 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
SN54AHC273
SN74AHC273
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
f
CL = 15 pF
75*
120*
65*
65
MHz
fmax
CL = 50 pF
50
75
45
45
MHz
tPHL
CLR
Q
CL = 15 pF
8.9*
13.6*
1*
16*
1
16
ns
tPLH
CLK
Q
CL = 15 pF
8.7*
13.6*
1*
16*
1
16
ns
tPHL
CLK
Q
CL = 15 pF
8.7*
13.6*
1*
16*
1
16
ns
tPHL
CLR
Q
CL = 50 pF
11.4
17.1
1
19.5
1
19.5
ns
tPLH
CLK
Q
CL = 50 pF
11.2
17.1
1
19.5
1
19.5
ns
tPHL
CLK
Q
CL = 50 pF
11.2
17.1
1
19.5
1
19.5
ns
tsk(o)
CL = 50 pF
1.5**
1.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
SN54AHC273
SN74AHC273
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
f
CL = 15 pF
120*
165*
100*
100
MHz
fmax
CL = 50 pF
80
110
70
70
MHz
tPHL
CLR
Q
CL = 15 pF
5.2*
8.5*
1*
10*
1
10
ns
tPLH
CLK
Q
CL = 15 pF
5.8*
9*
1*
10.5*
1
10.5
ns
tPHL
CLK
Q
CL = 15 pF
5.8*
9*
1*
10.5*
1
10.5
ns
tPHL
CLR
Q
CL = 50 pF
6.7
10.5
1
12
1
12
ns
tPLH
CLK
Q
CL = 50 pF
7.3
11
1
12.5
1
12.5
ns
tPHL
CLK
Q
CL = 50 pF
7.3
11
1
12.5
1
12.5
ns
tsk(o)
CL = 50 pF
1**
1
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
noise characteristics, V
CC
= 5 V, C
L
= 50 pF, T
A
= 25
C (see Note 4)
PARAMETER
SN74AHC273
UNIT
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.7
V
VOL(V)
Quiet output, minimum dynamic VOL
0.7
V
VOH(V)
Quiet output, minimum dynamic VOH
4.7
V
VIH(D)
High-level dynamic input voltage
3.5
V
VIL(D)
Low-level dynamic input voltage
1.5
V
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load,
f = 1 MHz
31
pF
SN54AHC273, SN74AHC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS376G JUNE 1997 REVISED JULY 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
50% VCC
VOL
+ 0.3 V
50% VCC
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST
S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr
3 ns, tf
3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL = 1 k
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
VOH
0.3 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
5962-9853001Q2A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
N / A for Pkg Type
5962-9853001QRA
ACTIVE
CDIP
J
20
1
TBD
Call TI
N / A for Pkg Type
5962-9853001QSA
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
SN74AHC273DBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
SN74AHC273DBR
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273DBRE4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273DGVR
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273DGVRE4
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273DW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273DWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273DWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74AHC273NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74AHC273NSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273NSRE4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273PWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273PWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
SN74AHC273PWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273PWRE4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC273PWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54AHC273FK
ACTIVE
LCCC
FK
20
1
TBD
Call TI
N / A for Pkg Type
SNJ54AHC273J
ACTIVE
CDIP
J
20
1
TBD
Call TI
N / A for Pkg Type
SNJ54AHC273W
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
Addendum-Page 1
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
Addendum-Page 2
MECHANICAL DATA
MLCC006B OCTOBER 1996
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
4040140 / D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MIN
MAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)
(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
13
14
15
16
18
17
11
10
8
9
7
5
4
3
2
0.020 (0,51)
0.010 (0,25)
6
1
28
26
27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MPDS006C FEBRUARY 1996 REVISED AUGUST 2000
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50
4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
1
12
24
13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
38
24
16
4,90
5,10
3,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins MO-153
14/16/20/56 Pins MO-194
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,90
7,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
20
16
6,50
6,50
14
0,05 MIN
5,90
5,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65
M
0,15
0
8
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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