SN54AHC594, SN74AHC594
8 BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS423F - JUNE 1998 - REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Operating Range 2-V to 5.5-V V
CC
D
8-Bit Serial-In, Parallel-Out Shift
Registers With Storage
D
Independent Direct Overriding Clears
on Shift and Storage Registers
D
Independent Clocks for Shift and
Storage Registers
D
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
description/ordering information
The 'AHC594 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Separate clocks and direct
overriding clear (SRCLR, RCLR) inputs are
provided on the shift and storage registers. A
serial (Q
H
) output is provided for cascading
purposes.
The shift register (SRCLK) and storage register
(RCLK) clocks are positive-edge triggered. If the
clocks are tied together, the shift register always
is one clock pulse ahead of the storage register.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP - N
Tube
SN74AHC594N
SN74AHC594N
SOIC - D
Tube
SN74AHC594D
AHC594
SOIC - D
Tape and reel
SN74AHC594DR
AHC594
-40
C to 85
C
SOP - NS
Tape and reel
SN74AHC594NSR
AHC594
-40 C to 85 C
SSOP - DB
Tape and reel
SN74AHC594DBR
HA594
TSSOP - PW
Tube
SN74AHC594PW
HA594
TSSOP - PW
Tape and reel
SN74AHC594PWR
HA594
CDIP - J
Tube
SNJ54AHC594J
SNJ54AHC594J
-55
C to 125
C
CFP - W
Tube
SNJ54AHC594W
SNJ54AHC594W
-55 C to 125 C
LCCC - FK
Tube
SNJ54AHC594FK
SNJ54AHC594FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54AHC594 . . . J OR W PACKAGE
SN74AHC594 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54AHC594 . . . FK PACKAGE
(TOP VIEW)
NC - No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
GND
V
CC
Q
A
SER
RCLR
RCLK
SRCLK
SRCLR
Q
H
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
SER
RCLR
NC
RCLK
SRCLK
Q
D
Q
E
NC
Q
F
Q
G
Q
NC
SRCLR
H
GND
NC
C
Q
B
V
CC
Q
A
Q
H
Q
SN54AHC594, SN74AHC594
8 BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS423F - JUNE 1998 - REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
FUNCTION
SER
SRCLK
SRCLR
RCLK
RCLR
FUNCTION
X
X
L
X
X
Shift register is cleared.
L
H
X
X
First stage of shift register goes low.
Other stages store the data of previous stage, respectively.
H
H
X
X
First stage of shift register goes high.
Other stages store the data of previous stage, respectively.
L
H
X
X
Shift register state is not changed.
X
X
X
X
L
Storage register is cleared.
X
X
X
H
Shift register data is stored in the storage register.
X
X
X
H
Storage register state is not changed.
SN54AHC594, SN74AHC594
8 BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS423F - JUNE 1998 - REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
R
3D
C3
1D
C1
R
R
3D
C3
2D
C2
R
R
3D
C3
2D
C2
R
R
3D
C3
2D
C2
R
R
3D
C3
2D
C2
R
R
3D
C3
2D
C2
R
R
3D
C3
2D
C2
R
R
3D
C3
2D
C2
R
13
12
10
11
14
15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
QH
RCLR
SRCLR
RCLK
SRCLK
SER
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
SN54AHC594, SN74AHC594
8 BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS423F - JUNE 1998 - REVISED SEPTEMBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing diagram
SRCLK
SER
RCLK
SRCLR
RCLR
QA
QB
QC
QD
QE
QF
QG
QH
QH
SN54AHC594, SN74AHC594
8 BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS423F - JUNE 1998 - REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
75 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
82
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
108
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AHC594
SN74AHC594
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2
5.5
2
5.5
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 3 V
2.1
2.1
V
VIH
High-level input voltage
VCC = 5.5 V
3.85
3.85
V
VCC = 2 V
0.5
0.5
VIL
Low-level input voltage
VCC = 3 V
0.9
0.9
V
VIL
Low-level input voltage
VCC = 5.5 V
1.65
1.65
V
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
-50
-50
m
A
IOH
High-level output current
VCC = 3.3 V
0.3 V
-4
-4
mA
IOH
High-level output current
VCC = 5 V
0.5 V
-8
-8
mA
VCC = 2 V
50
50
m
A
IOL
Low-level output current
VCC = 3.3 V
0.3 V
4
4
mA
IOL
Low-level output current
VCC = 5 V
0.5 V
8
8
mA
D
t/
D
v
Input transition rise or fall rate
VCC = 3.3 V
0.3 V
100
100
ns/V
D
t/
D
v
Input transition rise or fall rate
VCC = 5 V
0.5 V
20
20
ns/V
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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