SN54AHCT02, SN74AHCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS262I DECEMBER 1995 REVISED JANUARY 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
EPIC
TM
(Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
description
These devices contain four independent 2-input
NOR gates that perform the Boolean function
Y = A
S
B or Y = A + B in positive logic.
The SN54AHCT02 is characterized for operation
over the full military temperature range of 55
C
to 125
C. The SN74AHCT02 is characterized for
operation from 40
C to 85
C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A
B
Y
H
X
L
X
H
L
L
L
H
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1Y
1A
1B
2Y
2A
2B
GND
V
CC
4Y
4B
4A
3Y
3B
3A
SN54AHCT02 . . . J OR W PACKAGE
SN74AHCT02 . . . D, DB, DGV, N, OR PW PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4B
NC
4A
NC
3Y
1B
NC
2Y
NC
2A
1A
1Y
NC
3A
3B
V
4Y
2B
GND
NC
SN54AHCT02 . . . FK PACKAGE
(TOP VIEW)
CC
NC No internal connection
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54AHCT02, SN74AHCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS262I DECEMBER 1995 REVISED JANUARY 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
2
1A
3
1B
1Y
1
5
2A
6
2B
2Y
4
8
3A
9
3B
3Y
10
11
4A
12
4B
4Y
13
1
logic diagram (positive logic)
2
1A
3
1B
1Y
1
8
3A
9
3B
3Y
10
5
2A
6
2B
2Y
4
11
4A
12
4B
4Y
13
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
96
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
127
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
SN54AHCT02, SN74AHCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS262I DECEMBER 1995 REVISED JANUARY 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54AHCT02
SN74AHCT02
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
8
8
mA
IOL
Low-level output current
8
8
mA
t/
v
Input transition rise or fall rate
20
20
ns/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54AHCT02
SN74AHCT02
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VOH
IOH = 50
m
A
4 5 V
4.4
4.5
4.4
4.4
V
VOH
IOH = 8 mA
4.5 V
3.94
3.8
3.8
V
VOL
IOL = 50
m
A
4 5 V
0.1
0.1
0.1
V
VOL
IOL = 8 mA
4.5 V
0.36
0.44
0.44
V
II
VI = VCC or GND
0 V to 5.5 V
0.1
1*
1
m
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
2
20
20
m
A
ICC
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
1.35
1.5
1.5
mA
Ci
VI = VCC or GND
5 V
4
10
10
pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
SN54AHCT02
SN74AHCT02
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
A or B
Y
CL = 15 pF
2.4**
5.5**
1**
6.5**
1
6.5
ns
tPHL
A or B
Y
CL = 15 pF
3.5**
5.5**
1**
6.5**
1
6.5
ns
tPLH
A or B
Y
CL = 50 pF
3.4
7.5
1
8.5
1
8.5
ns
tPHL
A or B
Y
CL = 50 pF
4.5
7.5
1
8.5
1
8.5
ns
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
SN54AHCT02, SN74AHCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS262I DECEMBER 1995 REVISED JANUARY 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
noise characteristics, V
CC
= 5 V, C
L
= 50 pF, T
A
= 25
C (see Note 4)
PARAMETER
SN74AHCT02
UNIT
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
4.7
V
VIH(D)
High-level dynamic input voltage
2
V
VIL(D)
Low-level dynamic input voltage
0.8
V
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load,
f = 1 MHz
17
pF
SN54AHCT02, SN74AHCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS262I DECEMBER 1995 REVISED JANUARY 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
50% VCC
VOL
+ 0.3 V
50% VCC
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST
S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr
3 ns, tf
3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL = 1 k
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH
0.3 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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