SN54AHCT74, SN74AHCT74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS263N DECEMBER 1995 REVISED JULY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Inputs Are TTL-Voltage Compatible
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54AHCT74 . . . J OR W PACKAGE
SN74AHCT74 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
2Q
V
2CLR
1Q
GND
NC
SN54AHCT74 . . . FK PACKAGE
(TOP VIEW)
CC
NC No internal connection
SN74AHCT74 . . . RGY PACKAGE
(TOP VIEW)
1
14
7
8
2
3
4
5
6
13
12
11
10
9
2CLR
2D
2CLK
2PRE
2Q
1D
1CLK
1PRE
1Q
1Q
1CLR
2Q
V
GND
CC
description/ordering information
The 'AHCT74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN RGY
Tape and reel
SN74AHCT74RGYR
HB74
PDIP N
Tube
SN74AHCT74N
SN74AHCT74N
SOIC D
Tube
SN74AHCT74D
AHCT74
SOIC D
Tape and reel
SN74AHCT74DR
AHCT74
40
C to 85
C
SOP NS
Tape and reel
SN74AHCT74NSR
AHCT74
SSOP DB
Tape and reel
SN74AHCT74DBR
HB74
TSSOP
PW
Tube
SN74AHCT74PW
HB74
TSSOP PW
Tape and reel
SN74AHCT74PWR
HB74
TVSOP DGV
Tape and reel
SN74AHCT74DGVR
HB74
CDIP J
Tube
SNJ54AHCT74J
SNJ54AHCT74J
55
C to 125
C
CFP W
Tube
SNJ54AHCT74W
SNJ54AHCT74W
LCCC FK
Tube
SNJ54AHCT74FK
SNJ54AHCT74FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54AHCT74, SN74AHCT74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS263N DECEMBER 1995 REVISED JULY 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0
Q0
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic diagram, each flip-flop (positive logic)
TG
C
C
TG
C
TG
C
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
SN54AHCT74, SN74AHCT74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS263N DECEMBER 1995 REVISED JULY 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DB package
96
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DGV package
127
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): NS package
76
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package
47
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
SN54AHCT74
SN74AHCT74
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
8
8
mA
IOL
Low-level output current
8
8
mA
t/
v
Input transition rise or fall rate
20
20
ns/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54AHCT74, SN74AHCT74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS263N DECEMBER 1995 REVISED JULY 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54AHCT74
SN74AHCT74
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VOH
IOH = 50
m
A
4 5 V
4.4
4.5
4.4
4.4
V
VOH
IOH = 8 mA
4.5 V
3.94
3.8
3.8
V
VOL
IOL = 50
m
A
4 5 V
0.1
0.1
0.1
V
VOL
IOL = 8 mA
4.5 V
0.36
0.44
0.44
V
II
VI = 5.5 V or GND
0 V to 5.5 V
0.1
1*
1
m
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
2
20
20
m
A
ICC
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
1.35
1.5
1.5
mA
Ci
VI = VCC or GND
5 V
2
10
10
pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
PARAMETER
TA = 25
C
SN54AHCT74
SN74AHCT74
UNIT
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration
PRE or CLR low
5
5
5
ns
tw
Pulse duration
CLK
5
5
5
ns
t
Setup time before CLK
Data
5
5
5
ns
tsu
Setup time before CLK
PRE or CLR inactive
3.5
3.5
3.5
ns
th
Hold time, data after CLK
0
0
0
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
SN54AHCT74
SN74AHCT74
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
f
CL = 15 pF
100**
160**
80**
80
MHz
fmax
CL = 50 pF
80
140
65
65
MHz
tPLH
PRE or CLR
Q or Q
CL = 15 pF
7.6**
10.4**
1**
12**
1
12
ns
tPHL
PRE or CLR
Q or Q
CL = 15 pF
7.6**
10.4**
1**
12**
1
12
ns
tPLH
CLK
Q
Q
CL = 15 pF
5.8**
7.8**
1**
9**
1
9
ns
tPHL
CLK
Q or Q
CL = 15 pF
5.8**
7.8**
1**
9**
1
9
ns
tPLH
PRE
CLR
Q
Q
CL = 50 pF
8.1
11.4
1
13
1
13
ns
tPHL
PRE or CLR
Q or Q
CL = 50 pF
8.1
11.4
1
13
1
13
ns
tPLH
CLK
Q or Q
CL = 50 pF
6.3
8.8
1
10
1
10
ns
tPHL
CLK
Q or Q
CL = 50 pF
6.3
8.8
1
10
1
10
ns
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
SN54AHCT74, SN74AHCT74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS263N DECEMBER 1995 REVISED JULY 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
noise characteristics, V
CC
= 5 V, C
L
= 50 pF, T
A
= 25
C (see Note 5)
PARAMETER
SN74AHCT74
UNIT
PARAMETER
MIN
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
4
V
VIH(D)
High-level dynamic input voltage
2
V
VIL(D)
Low-level dynamic input voltage
0.8
V
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load,
f = 1 MHz
32
pF
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