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FEATURES
PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OE
1A
1B
GND
V
CC
2OE
2B
2A
DESCRIPTION/ORDERING INFORMATION
SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A OCTOBER 2003 REVISED APRIL 2005
Data and Control Inputs Provide Undershoot
Clamp Diodes
High-Bandwidth Data Path (up to 500 MHz
(1)
)
Low Power Consumption (I
CC
= 0.25 mA Typ)
5-V Tolerant I/Os With Device Powered Up or
Powered Down
V
CC
Operating Range From 2.3 V to 3.6 V
Low and Flat ON-State Resistance (r
on
)
Data I/Os Support 0- to 5-V Signaling Levels
Characteristics Over Operating Range
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
(r
on
= 3
Typ)
Control Inputs Can Be Driven by TTL or
Rail-to-Rail Switching on Data I/O Ports
5-V/3.3-V CMOS Outputs
0- to 5-V Switching With 3.3-V V
CC
I
off
Supports Partial-Power-Down Mode
Operation
0- to 3.3-V Switching With 2.5-V V
CC
Latch-Up Performance Exceeds 100 mA Per
Bidirectional Data Flow With Near-Zero
JESD 78, Class II
Propagation Delay
ESD Performance Tested Per JESD 22
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
2000-V Human-Body Model
(C
io(OFF)
= 3.5 pF Typ)
(A114-B, Class II)
Fast Switching Frequency (f
OE
= 20 MHz Max)
1000-V Charged-Device Model (C101)
Supports Both Digital and Analog
(1)
For additional information regarding the performance
Applications: USB Interface, Differential
characteristics of the CB3Q family, refer to the TI application
Signal Interface, Bus Isolation, Low-Distortion
report, CBT-C, CB3T, and CB3Q Signal-Switch Families,
literature number SCDA008.
Signal Gating
The SN74CB3Q3305 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of
the pass transistor, providing a low and flat ON-state resistance (r
on
). The low and flat ON-state resistance allows
for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device
also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus.
Specifically designed to support high-bandwidth applications, the SN74CB3Q3305 provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
The SN74CB3Q3305 is organized as two 1-bit switches with separate output-enable (1OE, 2OE) inputs. It can
be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is high, the associated 1-bit bus switch is
ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is low, the
associated 1-bit bus switch is OFF and a high-impedance state exists between the A and B ports.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
Tube
SN74CB3Q3305PW
40C to 85C
TSSOP PW
BU305
Tape and reel
SN74CB3Q3305PWR
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 20032005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
1A
1OE
SW
1B
2A
2OE
SW
2B
2
1
5
7
3
6
A
EN
(1)
B
(1) EN is the internal enable signal applied to the switch.
Charge
Pump
V
CC
SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A OCTOBER 2003 REVISED APRIL 2005
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry prevents damaging
current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
FUNCTION TABLE
(EACH BUS SWITCH)
INPUT
INPUT/OUTPUT
FUNCTION
OE
A
H
B
A port = B port
L
Z
Disconnect
LOGIC DIAGRAM (POSITIVE LOGIC)
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
2
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A OCTOBER 2003 REVISED APRIL 2005
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
CC
Supply voltage range
0.5
4.6
V
V
IN
Control input voltage range
(2) (3)
0.5
7
V
V
I/O
Switch I/O voltage range
(2) (3) (4)
0.5
7
V
I
IK
Control input clamp current
V
IN
< 0
50
mA
I
I/OK
I/O port clamp current
V
I/O
< 0
50
mA
I
I/O
ON-state switch current
(5)
64
mA
Continuous current through V
CC
or GND
100
mA
JA
Package thermal impedance
(6)
88
C/W
T
stg
Storage temperature range
65
150
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltages are with respect to ground, unless otherwise specified.
(3)
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4)
V
I
and V
O
are used to denote specific conditions for V
I/O
.
(5)
I
I
and I
O
are used to denote specific conditions for I
I/O
.
(6)
The package thermal impedance is calculated in accordance with JESD 51-7.
MIN
MAX
UNIT
V
CC
Supply voltage
2.3
3.6
V
V
CC
= 2.3 V to 2.7 V
1.7
5.5
V
IH
High-level control input voltage
V
V
CC
= 2.7 V to 3.6 V
2
5.5
V
CC
= 2.3 V to 2.7 V
0
0.7
V
IL
Low-level control input voltage
V
V
CC
= 2.7 V to 3.6 V
0
0.8
V
I/O
Data input/output voltage
0
5.5
V
T
A
Operating free-air temperature
40
85
C
(1)
All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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Electrical Characteristics
(1)
Switching Characteristics
SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A OCTOBER 2003 REVISED APRIL 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
(2)
MAX
UNIT
V
IK
V
CC
= 3.6 V,
I
I
= 18 mA
1.8
V
Control
I
IN
V
CC
= 3.6 V,
V
IN
= 0 to 5.5 V
1
A
inputs
V
O
= 0 to 5.5 V,
Switch OFF,
I
OZ
(3)
V
CC
= 3.6 V,
1
A
V
I
= 0,
V
IN
= V
CC
or GND
I
off
V
CC
= 0,
V
O
= 0 to 5.5 V,
V
I
= 0
1
A
I
I/O
= 0,
I
CC
V
CC
= 3.6 V,
V
IN
= V
CC
or GND
0.25
0.7
mA
Switch ON or OFF,
Control
I
CC
(4)
V
CC
= 3.6 V, One input at 3 V, Other inputs at V
CC
or GND
25
A
inputs
V
CC
= 3.6 V,
A and B ports open,
Per control
mA/
I
CCD
(5)
0.040
0.045
input
MHz
Control input switching at 50% duty cycle
Control
C
in
V
CC
= 3.3 V,
V
IN
= 5.5 V, 3.3 V, or 0
2.5
3.5
pF
inputs
Switch OFF,
C
io(OFF)
V
CC
= 3.3 V,
V
I/O
= 5.5 V, 3.3 V, or 0
3.5
5
pF
V
IN
= V
CC
or GND,
Switch ON,
C
io(ON)
V
CC
= 3.3 V,
V
I/O
= 5.5 V, 3.3 V, or 0
8
10.5
pF
V
IN
= V
CC
or GND,
V
I
= 0, I
O
= 30 mA
3
8
V
CC
= 2.3 V,
TYP at V
CC
= 2.5 V
V
I
= 1.7 V, I
O
= 15 mA
3.5
9
r
on
(6)
V
I
= 0, I
O
= 30 mA
3
6
V
CC
= 3 V
V
I
= 2.4 V, I
O
= 15 mA
3.5
8
(1)
V
IN
and I
IN
refer to control inputs. V
I
, V
O
, I
I
, and I
O
refer to data pins.
(2)
All typical values are at V
CC
= 3.3 V (unless otherwise noted), T
A
= 25C.
(3)
For I/O ports, the parameter I
OZ
includes the input leakage current.
(4)
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
CC
or GND.
(5)
This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see
Figure 2).
(6)
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
V
CC
= 2.5 V
V
CC
= 3.3 V
FROM
TO
0.2 V
0.3 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
f
OE
(1)
OE
A or B
10
20
MHz
t
pd
(2)
A or B
B or A
0.09
0.15
ns
t
en
OE
A or B
1
5
1
4.5
ns
t
dis
OE
A or B
1
4.5
1
5
ns
(1)
Maximum switching frequency for control input (V
O
> V
CC
, V
I
= 5 V, R
L
1 M
, C
L
= 0)
(2)
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
4
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0
2
4
6
8
10
12
14
16
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
r
on
- ON-State Resistance -
V
I
- V
TYPICAL r
on
vs
V
I
V
CC
= 3.3 V
T
A
= 25
C
I
O
= -15 mA
0
2
4
6
8
10
12
0
2
4
6
8
10
12
14
16
18
20
OE Switching Frequency - MHz
TYPICAL I
CC
vs
OE SWITCHING FREQUENCY
CCI
- mA
V
CC
= 3.3 V
T
A
= 25
C
A and B Ports Open
One OE Switching
SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A OCTOBER 2003 REVISED APRIL 2005
Figure 1. Typical r
on
vs V
I
Figure 2. Typical I
CC
vs OE Switching Frequency
5
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PARAMETER MEASUREMENT INFORMATION
V
OH
V
OL
C
L
(see Note A)
TEST CIRCUIT
S1
2
V
CC
Open
GND
R
L
R
L
t
PLH
t
PHL
Output
Waveform 1
S1 at 2
V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
V
CC
0 V
V
OH
V
OL
0 V
V
OL
+ V
V
OH
- V
0 V
Output
Control
(V
IN
)
V
CC
V
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
pd(s)
)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Z
O
= 50
, t
r
2.5 ns, t
f
2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd(s)
. The t
pd
propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
50
V
G1
V
CC
DUT
50
V
IN
50
V
G2
50
V
I
TEST
R
L
S1
V
C
L
2.5 V
0.2 V
3.3 V
0.3 V
V
CC
V
I
t
PHZ
/t
PZH
t
PLZ
/t
PZL
t
pd(s)
2.5 V
0.2 V
3.3 V
0.3 V
2.5 V
0.2 V
3.3 V
0.3 V
Open
Open
2
V
CC
2
V
CC
GND
GND
500
500
500
500
500
500
V
CC
or GND
V
CC
or GND
GND
GND
V
CC
V
CC
30 pF
50 pF
30 pF
50 pF
30 pF
50 pF
0.15 V
0.3 V
0.15 V
0.3 V
Output
Control
(V
IN
)
Input Generator
Input Generator
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
O
SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A OCTOBER 2003 REVISED APRIL 2005
Figure 3. Test Circuit and Voltage Waveforms
6
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74CB3Q3305DCURE4
ACTIVE
US8
DCU
8
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74CB3Q3305DCUR
ACTIVE
US8
DCU
8
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74CB3Q3305PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CB3Q3305PWE4
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CB3Q3305PWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CB3Q3305PWRE4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
Addendum-Page 1
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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2005, Texas Instruments Incorporated
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