SN74CB3T3384
10 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS159B - OCTOBER 2003 - REVISED MARCH 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Output Voltage Translation Tracks V
CC
D
Supports Mixed-Mode Signal Operation On
All Data I/O Ports
- 5-V Input Down To 3.3-V Output Level
Shift With 3.3-V V
CC
- 5-V/3.3-V Input Down To 2.5-V Output
Level Shift With 2.5-V V
CC
D
5-V-Tolerant I/Os With Device Powered-Up
or Powered-Down
D
Bidirectional Data Flow, With Near-Zero
Propagation Delay
D
Low ON-State Resistance (r
on
)
Characteristics (r
on
= 5
Typical)
D
Low Input/Output Capacitance Minimizes
Loading (C
io(OFF)
= 5 pF Typical)
D
Data and Control Inputs Provide
Undershoot Clamp Diodes
D
Low Power Consumption
(I
CC
= 40
A Max)
D
V
CC
Operating Range From 2.3 V to 3.6 V
D
Data I/Os Support 0 to 5-V Signaling Levels
(For Example: 0.8-V, 1.2-V, 1.5-V, 1.8-V,
2.5-V, 3.3-V, 5-V)
D
Control Inputs Can Be Driven by TTL or
5-V/3.3-V/2.5-V CMOS Outputs
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II)
- 1000-V Charged-Device Model (C101)
D
Supports Digital Applications: Level
Translation, Memory Interleaving, Bus
Isolation
D
Ideal for Low-Power Portable Equipment
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1OE
1B1
1A1
1A2
1B2
1B3
1A3
1A4
1B4
1B5
1A5
GND
V
CC
2B5
2A5
2A4
2B4
2B3
2A3
2A2
2B2
2B1
2A1
2OE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
description/ordering information
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC - DW
Tube
SN74CB3T3384DW
CB3T3384
SOIC - DW
Tape and reel
SN74CB3T3384DWR
CB3T3384
-40
C to 85
C
SSOP (QSOP) - DBQ
Tape and reel
SN74CB3T3384DBQR
CB3T3384
-40
C to 85
C
TSSOP - PW
Tube
SN74CB3T3384PW
KS384
TSSOP - PW
Tape and reel
SN74CB3T3384PWR
KS384
TVSOP - DGV
Tape and reel
SN74CB3T3384DGVR
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74CB3T3384
10 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS159B - OCTOBER 2003 - REVISED MARCH 2004
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The SN74CB3T3384 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r
on
),
allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O
ports by providing voltage translation that tracks V
CC
. The SN74CB3T3384 supports systems using 5-V TTL,
3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
VCC
VCC
5.5 V
0 V
NOTE A: If the input high voltage (VIH) level is greater than or equal to VCC - 1 V, and less than or equal to 5.5 V, the output high
voltage (VOH) level will be equal to approximately the VCC voltage level.
Input Voltages
Output Voltages
0 V
VCC - 1 V
VCC - 1 V
VCC
IN
OUT
CB3T
Figure 1. Typical DC-Voltage-Translation Characteristics
The SN74CB3T3384 is organized as two 5-bit bus switches with separate ouput-enable (1OE, 2OE) inputs. It
can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE is low, the associated 5-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using I
off
. The I
off
feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each 5-bit bus switch)
INPUT
INPUT/OUTPUT
FUNCTION
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
A port = B port
H
Z
Disconnect
SN74CB3T3384
10 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS159B - OCTOBER 2003 - REVISED MARCH 2004
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1A1
SW
1B1
1A5
1OE
SW
1B5
2A1
SW
2B1
2A5
2OE
SW
2B5
3
11
1
14
22
13
2
10
15
23
simplified schematic, each FET switch (SW)
VG
A
EN
B
Gate Voltage (VG) is approximately
equal to VCC + VT when the switch is ON
and VI
>
VCC + VT.
Control
Circuit
EN is the internal enable signal applied to the switch.
SN74CB3T3384
10 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS159B - OCTOBER 2003 - REVISED MARCH 2004
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input voltage range, V
IN
(see Notes 1 and 2)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch I/O voltage range, V
I/O
(see Notes 1, 2, and 3)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input clamp current, I
IK
(V
IN
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O port clamp current, I
I/OK
(V
I/O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON-state switch current, I
I/O
(see Note 4)
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND terminals
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 5): DBQ package
61
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
46
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
88
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN
MAX
UNIT
VCC
Supply voltage
2.3
3.6
V
VIH
High-level control input voltage
VCC = 2.3 V to 2.7 V
1.7
5.5
V
VIH
High-level control input voltage
VCC = 2.7 V to 3.6 V
2
5.5
V
VIL
Low-level control input voltage
VCC = 2.3 V to 2.7 V
0
0.7
V
VIL
Low-level control input voltage
VCC = 2.7 V to 3.6 V
0
0.8
V
VI/O
Data input/output voltage
0
5.5
V
TA
Operating free-air temperature
-40
85
C
NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74CB3T3384
10 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS159B - OCTOBER 2003 - REVISED MARCH 2004
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
VCC = 3 V,
II = -18 mA
-1.2
V
VOH
See Figures 3 and 4
IIN
Control inputs
VCC = 3.6 V,
VIN = 3.6 V to 5.5 V or GND
10
A
VCC = 3.6 V,
VI = VCC - 0.7 V to 5.5 V
20
II
VCC = 3.6 V,
Switch ON,
V
= GND
VI = 0.7 V to VCC - 0.7 V
-40
A
II
Switch ON,
VIN = GND
VI = 0 to 0.7 V
5
A
IOZ
VCC = 3.6 V,
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC
10
A
Ioff
VCC = 0,
VO = 0 to 5.5 V,
VI = 0
10
A
ICC
VCC = 3.6 V,
II/O = 0,
VI = VCC or GND
40
A
ICC
II/O = 0,
Switch ON or OFF,
VIN = VCC or GND
VI = 5.5 V
40
A
ICC
Control inputs
VCC = 3 V to 3.6 V,
One input at VCC - 0.6 V,
Other inputs at VCC or GND
300
A
Cin
Control inputs
VCC = 3.3 V,
VIN = VCC or GND
3
pF
Cio(OFF)
VCC = 3.3 V,
VI/O = 5.5 V, 3.3 V, or GND,
Switch OFF,
VIN = VCC
5
pF
Cio(ON)
VCC = 3.3 V,
Switch ON,
VI/O = 5.5 V or 3.3 V
4
pF
Cio(ON)
CC
Switch ON,
VIN = GND
VI/O = GND
12
pF
VCC = 2.3 V,
TYP at VCC = 2.5 V,
IO = 24 mA
5
8
ron
CC
TYP at VCC = 2.5 V,
VI = 0
IO = 16 mA
5
8
ron
VCC = 3 V,
IO = 64 mA
5
7
VCC = 3 V,
VI = 0
IO = 32 mA
5
7
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25
C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the
lower of the voltages of the two (A or B) terminals.
SN74CB3T3384
10 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS159B - OCTOBER 2003 - REVISED MARCH 2004
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
0.2 V
VCC = 3.3 V
0.3 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
tpd
A or B
B or A
0.15
0.25
ns
ten
OE
A or B
1
10.5
1
7.5
ns
tdis
OE
A or B
1
6.5
1
8
ns
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
SN74CB3T3384
10 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS159B - OCTOBER 2003 - REVISED MARCH 2004
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOH
VOL
CL
(see Note A)
TEST CIRCUIT
S1
2
VCC
Open
GND
RL
RL
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + V
VOH - V
0 V
VCC
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
50
VG1
VCC
DUT
50
VIN
50
VG2
50
VI
TEST
RL
S1
V
CL
VCC
VI
tPHZ/tPZH
tPLZ/tPZL
2.5 V
0.2 V
3.3 V
0.3 V
2.5 V
0.2 V
3.3 V
0.3 V
2
VCC
2
VCC
Open
Open
500
500
500
500
GND
GND
3.6 V
5.5 V
30 pF
50 pF
30 pF
50 pF
0.15 V
0.3 V
0.15 V
0.3 V
Output
Control
(VIN)
Input Generator
Input Generator
VCC/2
VCC/2
VCC/2
VCC/2
VO
Figure 2. Test Circuit and Voltage Waveforms
SN74CB3T3384
10 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS159B - OCTOBER 2003 - REVISED MARCH 2004
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
V - Output V
oltage - V
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
O
VI - Input Voltage - V
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
VI - Input Voltage - V
0.0
1.0
2.0
3.0
4.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0.0
1.0
2.0
3.0
4.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VCC = 3 V
IO = 1
A
TA = 25
C
VCC = 2.3 V
IO = 1
A
TA = 25
C
V - Output V
oltage - V
O
Figure 3. Data Output Voltage vs Data Input Voltage
SN74CB3T3384
10 BIT FET BUS SWITCH
2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS159B - OCTOBER 2003 - REVISED MARCH 2004
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (continued)
1.5
2.0
2.5
3.0
3.5
4.0
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
1.5
2.0
2.5
3.0
3.5
4.0
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
1.5
2.0
2.5
3.0
3.5
4.0
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
V - Output V
oltage High - V
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
OH
VCC - Supply Voltage - V
VCC = 2.3 V ~ 3.6 V
VI = 5.5 V
TA = 85
C
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
VCC - Supply Voltage - V
VCC = 2.3 V ~ 3.6 V
VI = 5.5 V
TA = 25
C
V - Output V
oltage High - V
OH
100
A
8 mA
16 mA
24 mA
100
A
8 mA
16 mA
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
VCC - Supply Voltage - V
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = -40
C
V - Output V
oltage High - V
OH
100
A
8 mA
16 mA
24 mA
24 mA
Figure 4. V
OH
Values
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74CB3T3384DBQRE4
ACTIVE
SSOP/
QSOP
DBQ
24
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74CB3T3384DBQR
ACTIVE
SSOP/
QSOP
DBQ
24
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74CB3T3384DGVR
PREVIEW
TVSOP
DGV
24
2000
TBD
Call TI
Call TI
SN74CB3T3384DW
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CB3T3384DWE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CB3T3384DWR
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CB3T3384DWRE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CB3T3384PW
ACTIVE
TSSOP
PW
24
60
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CB3T3384PWE4
ACTIVE
TSSOP
PW
24
60
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CB3T3384PWR
ACTIVE
TSSOP
PW
24
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CB3T3384PWRE4
ACTIVE
TSSOP
PW
24
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jun-2005
Addendum-Page 1
MECHANICAL DATA
MPDS006C FEBRUARY 1996 REVISED AUGUST 2000
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50
4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
1
12
24
13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
38
24
16
4,90
5,10
3,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins MO-153
14/16/20/56 Pins MO-194
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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