SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES349C JUNE 2001 REVISED NOVEMBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
TI-OPC
Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D
OEC
Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
D
LVTTL Interfaces Are 5-V Tolerant
D
High-Drive GTLP Outputs (100 mA)
D
LVTTL Outputs (24 mA/24 mA)
D
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D
I
off
, Power-Up 3-State, and BIAS V
CC
Support Live Insertion
D
Polarity Control Selects True or
Complementary Outputs
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
description
The SN74GTLP1395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require
individual output-enable and true/complement controls. The device allows for transparent and inverted
transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback
path for control and diagnostics monitoring. The device provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to
work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times
faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V),
reduced input threshold levels, improved differential input, OEC
circuitry, and TI-OPC
circuitry. Improved
GTLP OEC and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several
backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent
load impedance down to 11
.
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLP1395 is given only at the preferred higher noise margin GTLP, but the
user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP (V
TT
= 1.5 V
and V
REF
= 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI
application reports, Texas Instruments GTLP Frequently Asked Questions,
literature number SCEA019, and
GTLP in BTL Applications, literature number SCEA017.
Copyright
2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGV, DW, OR PW PACKAGE
(TOP VIEW)
1Y
1T/C
2Y
GND
1OEAB
V
CC
1A
GND
2A
2OEAB
1OEBY
2T/C
2OEBY
GND
1B
ERC
2B
GND
V
REF
BIAS V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OEC and TI-OPC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES349C JUNE 2001 REVISED NOVEMBER 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL or 5-V CMOS devices. V
REF
is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly
terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This
improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between low and high adjusts the B-port output rise and fall times.
This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
terminal assignments
1
2
3
4
A
1T/C
1Y
1OEBY
2T/C
B
GND
GND
2Y
2OEBY
C
VCC
1OEAB
ERC
1B
D
GND
GND
1A
2B
E
2OEAB
2A
BIAS VCC
VREF
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC
DW
Tube
SN74GTLP1395DW
GTLP1395
SOIC DW
Tape and reel
SN74GTLP1395DWR
GTLP1395
40
C to 85
C
TSSOP PW
Tape and reel
SN74GTLP1395PWR
GP395
TVSOP DGV
Tape and reel
SN74GTLP1395DGVR
GP395
VFBGA GQN
Tape and reel
SN74GTLP1395GQNR
GP395
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
GQN PACKAGE
(TOP VIEW)
1
2
3
4
A
B
C
D
E
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES349C JUNE 2001 REVISED NOVEMBER 2001
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional description
The output-enable (1OEAB, 1OEBY) and polarity-control (1T/C) inputs control 1A, 1B, and 1Y. 2OEAB, 2OEBY,
and 2T/C control 2A, 2B, and 2Y.
OEAB controls the activity of the B port. When OEAB is low, the B-port output is active. When OEAB is high,
the B-port output is disabled.
A separate LVTTL A input and Y output provide a feedback path for control and diagnostics monitoring. OEBY
controls the Y output. When OEBY is low, the Y output is active. When OEBY is high, the Y output is disabled.
T/C selects polarity of data transmission in both directions. When T/C is high, data transmission is true, and
A data goes to the B bus and B data goes to the Y bus. When T/C is low, data transmission is complementary,
and inverted A data goes to the B bus and inverted B data goes to the Y bus.
Function Tables
OUTPUT CONTROL
INPUTS
OUTPUT
MODE
T/C
OEAB
OEBY
OUTPUT
MODE
X
H
H
Z
Isolation
H
L
H
A data to B bus
True transparent
H
H
L
B data to Y bus
True transparent
H
L
L
A data to B bus, B data to Y bus
True transparent
with feedback path
L
L
H
Inverted A data to B bus
Inverted transparent
L
H
L
Inverted B data to Y bus
Inverted transparent
L
L
L
Inverted A data to B bus,
Inverted B data to Y bus
Inverted transparent
with feedback path
OUTPUT EDGE-RATE CONTROL (ERC)
INPUT
ERC
LOGIC LEVEL
OUTPUT
B-PORT
EDGE RATE
H
Slow
L
Fast
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES349C JUNE 2001 REVISED NOVEMBER 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1OEAB
1T/C
1OEBY
5
2
20
ERC
15
1A
7
1Y
1
VREF
12
2A
9
2Y
3
1B
16
2B
14
2OEBY
18
2T/C
19
2OEAB
10
Pin numbers shown are for the DGV, DW, and PW packages.
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES349C JUNE 2001 REVISED NOVEMBER 2001
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
and BIAS V
CC
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1): A inputs, ERC, and control inputs
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . .
B port and V
REF
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1): Y outputs
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
: Y outputs
48 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
(see Note 2)
48 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DGV package
92
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQN package
78
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
83
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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