SN54HC03, SN74HC03
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
WITH OPEN-DRAIN OUTPUTS
SCLS077D MARCH 1984 REVISED AUGUST 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Wide Operating Voltage Range of 2 V to 6 V
D
Outputs Can Drive Up To 10 LSTTL Loads
D
Low Power Consumption, 20-
A Max I
CC
D
Typical t
pd
= 8 ns
D
4-mA Output Drive at 5 V
D
Low Input Current of 1
A Max
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
SN54HC03 . . . J OR W PACKAGE
SN74HC03 . . . D, N, OR NS PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
1B
1A
NC
3Y
3A
V
4B
2Y
GND
NC
SN54HC03 . . . FK PACKAGE
(TOP VIEW)
CC
NC No internal connection
description/ordering information
The 'HC03 devices contain four independent 2-input NAND gates. They perform the Boolean function
Y = A
B or Y = A + B in positive logic. The open-drain outputs require pullup resistors to perform correctly. They
may be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND
functions.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
40 C to 85 C
PDIP N
Tube of 25
SN74HC03N
SN74HC03N
40 C to 85 C
SOIC D
Tube of 50
SN74HC03D
HC03
40
C to 85
C
SOIC D
Reel of 2500
SN74HC03DR
HC03
Reel of 250
SN74HC03DT
SOP NS
Reel of 2000
SN74HC03NSR
HC03
55 C to 125 C
CDIP J
Tube of 25
SNJ54HC03J
SNJ54HC03J
55
C to 125
C
CFP W
Tube of 150
SNJ54HC03W
SNJ54HC03W
LCCC FK
Tube of 55
SNJ54HC03FK
SNJ54HC03FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A
B
OUTPUT
Y
H
H
L
L
X
H
X
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC03, SN74HC03
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
WITH OPEN-DRAIN OUTPUTS
SCLS077D MARCH 1984 REVISED AUGUST 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
76
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC03
SN74HC03
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
2
5
6
V
V
High-level input voltage
VCC = 2 V
1.5
1.5
V
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
IH
VCC = 6 V
4.2
4.2
V
Low-level input voltage
VCC = 2 V
0.5
0.5
V
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35
V
IL
VCC = 6 V
1.8
1.8
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
t/ v
Input transition rise/fall time
VCC = 2 V
1000
1000
ns
t/
v
Input transition rise/fall time
VCC = 4.5 V
500
500
ns
VCC = 6 V
400
400
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54HC03, SN74HC03
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
WITH OPEN-DRAIN OUTPUTS
SCLS077D MARCH 1984 REVISED AUGUST 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HC03
SN74HC03
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
IOH
VI = VIH or VIL,
VO = VCC
6 V
0.01
0.5
10
5
A
V
V = V
or V
I
= 20 A
2 V
0.002
0.1
0.1
0.1
V
V
V = V
or V
IOL = 20
A
4.5 V
0.001
0.1
0.1
0.1
V
VOL
VI = VIH or VIL
OL
6 V
0.001
0.1
0.1
0.1
V
OL
I
IH
IL
IOL = 4 mA
4.5 V
0.17
0.26
0.4
0.33
IOL = 5.2 mA
6 V
0.15
0.26
0.4
0.33
II
VI = VCC or 0
6 V
0.1
100
1000
1000
nA
ICC
VI = VCC or 0,
IO = 0
6 V
2
40
20
A
Ci
2 V to 6 V
3
10
10
10
pF
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HC03
SN74HC03
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
t
A or B
Y
2 V
60
105
155
131
ns
tPLH
A or B
Y
4.5 V
13
25
36
31
ns
PLH
6 V
10
23
31
27
t
A or B
Y
2 V
50
100
150
125
ns
tPHL
A or B
Y
4.5 V
10
20
30
25
ns
PHL
6 V
8
17
25
21
t
Y
2 V
38
75
110
95
ns
tf
Y
4.5 V
8
15
22
19
ns
f
6 V
6
13
19
16
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per gate
No load
20
pF
SN54HC03, SN74HC03
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
WITH OPEN-DRAIN OUTPUTS
SCLS077D MARCH 1984 REVISED AUGUST 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%
10%
10%
90%
VCC
VOH
VOL
0 V
tf
Input
In-Phase
Output
50%
tPLH
tPHL
50%
10%
10%
90%
VOH
VOL
tf
tPHL
tPLH
Out-of-Phase
Output
LOAD CIRCUIT
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
VCC
RL = 1 k
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
1 MHz, ZO = 50
, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
50%
50%
10%
10%
90%
90%
VCC
0 V
tr
tf
Input
Figure 1. Load Circuit and Voltage Waveforms
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