SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103E MARCH 1984 REVISED JULY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Wide Operating Voltage Range of 2 V to 6 V
D
High-Current 3-State Outputs Interface
Directly With System Bus or Can Drive Up
To 15 LSTTL Loads
D
Low Power Consumption, 80-
A Max I
CC
D
Typical t
pd
= 11 ns
D
6-mA Output Drive at 5 V
D
Low Input Current of 1
A Max
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1A
1OE
NC
3Y
3A
V
4OE
2Y
GND
NC
SN54HC126 . . . FK PACKAGE
(TOP VIEW)
CC
NC No internal connection
SN54HC126 . . . J OR W PACKAGE
SN74HC126 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
These quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled
when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup
resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
40 C to 85 C
PDIP N
Tube of 25
SN74HC126N
SN74HC126N
40 C to 85 C
SOIC D
Tube of 50
SN74HC126D
HC126
40 C to 85 C
SOIC D
Reel of 2500
SN74HC126DR
HC126
40 C to 85 C
Reel of 250
SN74HC126DT
40
C to 85
C
SOP NS
Reel of 2000
SN74HC126NSR
HC126
SSOP DB
Reel of 2000
SN74HC126DBR
HC126
TSSOP PW
Tube of 90
SN74HC126PW
HC126
TSSOP PW
Reel of 2000
SN74HC126PWR
HC126
Reel of 250
SN74HC126PWT
55 C to 125 C
CDIP J
Tube of 25
SNJ54HC126J
SNJ54HC126J
55
C to 125
C
CFP W
Tube of 150
SNJ54HC126W
SNJ54HC126W
LCCC FK
Tube of 55
SNJ54HC126FK
SNJ54HC126FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103E MARCH 1984 REVISED JULY 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
logic diagram (positive logic)
1
1OE
2
1A
1Y
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
3
4
2OE
5
2A
2Y
6
10
3OE
9
3A
3Y
8
13
4OE
12
4A
4Y
11
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
35 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
70 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
96
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
76
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103E MARCH 1984 REVISED JULY 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HC126
SN74HC126
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
2
5
6
V
V
High-level input voltage
VCC = 2 V
1.5
1.5
V
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
IH
VCC = 6 V
4.2
4.2
V
Low-level input voltage
VCC = 2 V
0.5
0.5
V
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35
V
IL
VCC = 6 V
1.8
1.8
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
t/ v
Input transition rise/fall time
VCC = 2 V
1000
1000
ns
t/
v
Input transition rise/fall time
VCC = 4.5 V
500
500
ns
VCC = 6 V
400
400
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HC126
SN74HC126
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
V
V = V
or V
I
= 20 A
2 V
1.9
1.998
1.9
1.9
V
V
V = V
or V
IOH = 20
A
4.5 V
4.4
4.499
4.4
4.4
V
VOH
VI = VIH or VIL
OH
6 V
5.9
5.999
5.9
5.9
V
OH
I
IH
IL
IOH = 6 mA
4.5 V
3.98
4.3
3.7
3.84
IOH = 7.8 mA
6 V
5.48
5.8
5.2
5.34
V
V = V
or V
I
= 20 A
2 V
0.002
0.1
0.1
0.1
V
V
V = V
or V
IOL = 20
A
4.5 V
0.001
0.1
0.1
0.1
V
VOL
VI = VIH or VIL
OL
6 V
0.001
0.1
0.1
0.1
V
OL
I
IH
IL
IOL = 6 mA
4.5 V
0.17
0.26
0.4
0.33
IOL = 7.8 mA
6 V
0.15
0.26
0.4
0.33
II
VI = VCC or 0
6 V
0.1
100
1000
1000
nA
IOZ
VO = VCC or 0
6 V
0.01
0.5
10
5
A
ICC
VI = VCC or 0,
IO = 0
6 V
8
160
80
A
Ci
2 V to 6 V
3
10
10
10
pF
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103E MARCH 1984 REVISED JULY 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HC126
SN74HC126
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
t
A
Y
2 V
47
120
180
150
ns
tpd
A
Y
4.5 V
14
24
36
30
ns
pd
6 V
11
20
31
26
t
OE
Y
2 V
57
120
180
150
ns
ten
OE
Y
4.5 V
16
24
36
30
ns
en
6 V
12
20
31
26
t
OE
Y
2 V
35
120
180
150
ns
tdis
OE
Y
4.5 V
17
24
36
30
ns
dis
6 V
15
20
31
26
t
Any
2 V
28
60
90
75
ns
tt
Any
4.5 V
8
12
18
15
ns
t
6 V
6
10
15
13
switching characteristics over recommended operating free-air temperature range, C
L
= 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HC126
SN74HC126
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
t
A
Y
2 V
67
150
225
188
ns
tpd
A
Y
4.5 V
19
30
45
38
ns
pd
6 V
15
25
39
33
t
OE
Y
2 V
100
135
202
169
ns
ten
OE
Y
4.5 V
20
27
40
36
ns
en
6 V
17
23
36
30
t
Any
2 V
45
210
315
265
ns
tt
Any
4.5 V
17
42
63
53
ns
t
6 V
13
36
53
45
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per gate
No load
45
pF
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103E MARCH 1984 REVISED JULY 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
50%
50%
10%
10%
90%
90%
VCC
0 V
tr
tf
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%
50%
10%
10%
90%
90%
VCC
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
50%
tPLH
tPHL
50%
50%
10%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
10%
90%
VCC
VCC
VOL
0 V
Output
Control
Output
Waveform 1
(See Note B)
tPZL
tPLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOH
0 V
50%
50%
tPZH
tPHZ
Output
Waveform 2
(See Note B)
Test
Point
From Output
Under Test
CL
(see Note A)
RL
VCC
S1
S2
LOAD CIRCUIT
PARAMETER
CL
tPZH
tpd or tt
tdis
ten
tPZL
tPHZ
tPLZ
1 k
1 k
50 pF
or
150 pF
50 pF
Open
Closed
RL
S1
Closed
Open
S2
Open
Closed
Closed
Open
50 pF
or
150 pF
Open
Open
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
1 MHz, ZO = 50
, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
50%
50%
Figure 1. Load Circuit and Voltage Waveforms
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