SN54HC132, SN74HC132
QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS034C DECEMBER 1982 REVISED MAY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Operation From Very Slow Input
Transitions
D
Temperature-Compensated Threshold
Levels
D
High Noise Immunity
D
Same Pinouts as 'HC00
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and Standard
Plastic (N) and Ceramic (J) 300-mil DIPs
description
Each circuit functions as a NAND gate, but
because of the Schmitt action, it has different input
threshold levels for positive- and negative-going
signals. The 'HC132 perform the Boolean function
Y = A
B or Y = A + B in positive logic.
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean jitter-free output signals.
The SN54HC132 is characterized for operation
over the full military temperature range of 55
C
to 125
C. The SN74HC132 is characterized for
operation from 40
C to 85
C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A
B
Y
H
H
L
L
X
H
X
L
H
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
SN54HC132 . . . J OR W PACKAGE
SN74HC132 . . . D, DB, OR N PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
1B
1A
NC
3Y
3A
V
4B
2Y
GND
NC
SN54HC132 . . . FK PACKAGE
(TOP VIEW)
CC
NC No internal connection
SN54HC132, SN74HC132
QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS034C DECEMBER 1982 REVISED MAY 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
1
1A
2
1B
1Y
3
4
2A
5
2B
2Y
6
9
3A
10
3B
3Y
8
12
4A
13
4B
4Y
11
&
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, and W packages.
logic diagram (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
127
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
158
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
78
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
SN54HC132, SN74HC132
QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS034C DECEMBER 1982 REVISED MAY 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
SN54HC132
SN74HC132
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
2
5
6
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VCC = 6 V
4.2
4.2
VCC = 2 V
0
0.5
0
0.5
VIL
Low-level input voltage
VCC = 4.5 V
0
1.35
0
1.35
V
VCC = 6 V
0
1.8
0
1.8
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
TA
Operating free-air temperature
55
125
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HC132
SN74HC132
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
1.9
1.998
1.9
1.9
IOH = 20
A
4.5 V
4.4
4.499
4.4
4.4
VOH
VI = VIH or VIL
6 V
5.9
5.999
5.9
5.9
V
IOH = 4 mA
4.5 V
3.98
4.3
3.7
3.84
IOH = 5.2 mA
6 V
5.48
5.8
5.2
5.34
2 V
0.002
0.1
0.1
0.1
IOL = 20
A
4.5 V
0.001
0.1
0.1
0.1
VOL
VI = VIH or VIL
6 V
0.001
0.1
0.1
0.1
V
IOL = 4 mA
4.5 V
0.17
0.26
0.4
0.33
IOL = 5.2 mA
6 V
0.15
0.26
0.4
0.33
2 V
0.7
1.2
1.5
0.7
1.5
0.7
1.5
VT+
4.5 V
1.55
2.5
3.15
1.55
3.15
1.55
3.15
V
6 V
2.1
3.3
4.2
2.1
4.2
2.1
4.2
2 V
0.3
0.6
1
0.3
1
0.3
1
VT
4.5 V
0.9
1.6
2.45
0.9
2.45
0.9
2.45
V
6 V
1.2
2
3.2
1.2
3.2
1.2
3.2
2 V
0.2
0.6
1.2
0.2
1.2
0.2
1.2
VT+ VT
4.5 V
0.4
0.9
2.1
0.4
2.1
0.4
2.1
V
6 V
0.5
1.3
2.5
0.5
2.5
0.5
2.5
II
VI = VCC or 0
6 V
0.1
100
1000
1000
nA
ICC
VI = VCC or 0,
IO = 0
6 V
2
40
20
A
Ci
2 V to 6 V
3
10
10
10
pF
SN54HC132, SN74HC132
QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS034C DECEMBER 1982 REVISED MAY 1997
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HC132
SN74HC132
UNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
60
120
186
156
tpd
A or B
Y
4.5 V
18
25
37
31
ns
6 V
14
21
32
27
2 V
28
75
110
95
tt
Any
4.5 V
8
15
22
19
ns
6 V
6
13
19
16
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per gate
No load
20
pF
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
50%
50%
10%
10%
90%
90%
VCC
0 V
tr
tf
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%
50%
10%
10%
90%
90%
VCC
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
50%
tPLH
tPHL
50%
50%
10%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
1 MHz, ZO = 50
, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright
1998, Texas Instruments Incorporated
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