SN54HC174, SN74HC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS119B DECEMBER 1982 REVISED MAY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Contain Six Flip-Flops With Single-Rail
Outputs
D
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
D
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These monolithic positive-edge-triggered D-type
flip-flops have a direct clear (CLR) input.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going edge of
CLK. When CLK is at either the high or low level,
the D input has no effect at the output.
The SN54HC174 is characterized for operation
over the full military temperature range of 55
C
to 125
C. The SN74HC174 is characterized for
operation from 40
C to 85
C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
CLR
CLK
D
Q
L
X
X
L
H
H
H
H
L
L
H
L
X
Q0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54HC174 . . . J OR W PACKAGE
SN74HC174 . . . D OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
6D
5D
NC
5Q
4D
1D
2D
NC
2Q
3D
SN54HC174 . . . FK PACKAGE
(TOP VIEW)
1Q
CLR
NC
CLK
4Q
6Q
3Q
GND
NC
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
1Q
1D
2D
2Q
3D
3Q
GND
V
CC
6Q
6D
5D
5Q
4D
4Q
CLK
NC No internal connection
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54HC174, SN74HC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS119B DECEMBER 1982 REVISED MAY 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
R
1
9
CLK
C1
1D
3
1D
4
2D
6
3D
11
4D
13
5D
14
6D
1Q
2
2Q
5
3Q
7
4Q
10
5Q
12
6Q
15
CLR
logic diagram (positive logic)
1D
C1
R
To Five Other Channels
1
9
3
2
CLR
CLK
1D
1Q
Pin numbers shown are for the D, J, N, and W packages.
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
78
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
SN54HC174, SN74HC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS119B DECEMBER 1982 REVISED MAY 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
SN54HC174
SN74HC174
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
2
5
6
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VCC = 6 V
4.2
4.2
VCC = 2 V
0
0.5
0
0.5
VIL
Low-level input voltage
VCC = 4.5 V
0
1.35
0
1.35
V
VCC = 6 V
0
1.8
0
1.8
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
0
1000
0
1000
tt
Input transition (rise and fall) time
VCC = 4.5 V
0
500
0
500
ns
VCC = 6 V
0
400
0
400
TA
Operating free-air temperature
55
125
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HC174
SN74HC174
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
1.9
1.998
1.9
1.9
IOH = 20
A
4.5 V
4.4
4.499
4.4
4.4
VOH
VI = VIH or VIL
6 V
5.9
5.999
5.9
5.9
V
IOH = 4 mA
4.5 V
3.98
4.3
3.7
3.84
IOH = 5.2 mA
6 V
5.48
5.8
5.2
5.34
2 V
0.002
0.1
0.1
0.1
IOL = 20
A
4.5 V
0.001
0.1
0.1
0.1
VOL
VI = VIH or VIL
6 V
0.001
0.1
0.1
0.1
V
IOL = 4 mA
4.5 V
0.17
0.26
0.4
0.33
IOL = 5.2 mA
6 V
0.15
0.26
0.4
0.33
II
VI = VCC or 0
6 V
0.1
100
1000
1000
nA
ICC
VI = VCC or 0,
IO = 0
6 V
8
160
80
A
Ci
2 V to 6 V
3
10
10
10
pF
SN54HC174, SN74HC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS119B DECEMBER 1982 REVISED MAY 1997
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25
C
SN54HC174
SN74HC174
UNIT
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
0
6
0
4.2
0
5
fclock
Clock frequency
4.5 V
0
31
0
21
0
25
MHz
6 V
0
36
0
25
0
29
2 V
80
120
100
CLR low
4.5 V
16
24
20
t
Pulse duration
6 V
14
20
17
ns
tw
Pulse duration
2 V
80
120
100
ns
CLK high or low
4.5 V
16
24
20
6 V
14
20
17
2 V
100
150
125
Data
4.5 V
20
30
25
t
Setup time before CLK
6 V
17
25
21
ns
tsu
Setup time before CLK
2 V
100
150
125
ns
CLR inactive
4.5 V
20
30
25
6 V
17
25
21
2 V
0
0
0
th
Hold time, data after CLK
4.5 V
0
0
0
ns
6 V
0
0
0
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HC174
SN74HC174
UNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
6
9
4.2
5
fmax
4.5 V
31
44
21
25
MHz
6 V
36
50
25
29
2 V
58
160
240
200
CLR
Any
4.5 V
17
32
48
40
t d
6 V
14
27
41
34
ns
tpd
2 V
58
160
240
200
ns
CLK
Any
4.5 V
17
32
48
40
6 V
14
27
41
34
2 V
38
75
110
90
tt
Any
4.5 V
8
15
22
19
ns
6 V
6
13
19
16
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per flip-flop
No load
27
pF
SN54HC174, SN74HC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS119B DECEMBER 1982 REVISED MAY 1997
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%
50%
10%
10%
90%
90%
VCC
VCC
0 V
0 V
tr
tf
Reference
Input
Data
Input
50%
High-Level
Pulse
50%
VCC
0 V
50%
50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%
50%
10%
10%
90%
90%
VCC
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
50%
tPLH
tPHL
50%
50%
10%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
1 MHz, ZO = 50
, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
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