SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B DECEMBER 1982 REVISED MAY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Single Down/Up Count-Control Line
D
Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
D
Fully Synchronous in Count Modes
D
Asynchronously Presettable With Load
Control
D
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
The 'HC191 are 4-bit synchronous, reversible,
up/down binary counters. Synchronous counting
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincident with each other when
instructed by the steering logic. This mode of
operation eliminates the output counting spikes
normally associated with asynchronous (ripple-
clock) counters.
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of the clock (CLK)
input if the count-enable (CTEN) input is low. A
high at CTEN inhibits counting. The direction of
the count is determined by the level of the
down/up (D/U) input. When D/U is low, the counter
counts up, and when D/U is high, it counts down.
These counters feature a fully independent clock circuit. Change at the control (CTEN and D/U) inputs that
modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter is dictated solely by the condition meeting the stable setup and hold times.
These counters are fully programmable; that is, each of the outputs can be preset to either level by placing a
low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with
the data inputs independently of the level of CLK. This feature allows the counters to be used as modulo-N
dividers by simply modifying the count length with the preset inputs.
Two outputs are available to perform the cascading function: ripple clock (RCO) and maximum/minimum
(MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one
complete cycle of the clock while the count is zero (all outputs low) counting down, or maximum (9 or 15)
counting up. RCO produces a low-level output pulse under those same conditions, but only while CLK is low.
The counters can be easily cascaded by feeding RCO to CTEN of the succeeding counter if parallel clocking
is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed
operation.
The SN54HC191 is characterized for operation over the full military temperature range of 55
C to 125
C. The
SN74HC191 is characterized for operation from 40
C to 85
C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
Q
B
Q
A
CTEN
D/U
Q
C
Q
D
GND
V
CC
A
CLK
RCO
MAX/MIN
LOAD
C
D
SN54HC191 . . . J OR W PACKAGE
SN74HC191 . . . D OR N PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
CLK
RCO
NC
MAX/MIN
LOAD
Q
A
CTEN
NC
D/U
Q
C
Q
B
NC
D
C
V
A
D
GND
NC
SN54HC191 . . . FK PACKAGE
(TOP VIEW)
NC No internal connection
B
CC
Q
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B DECEMBER 1982 REVISED MAY 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
CTRDIV16
G1
4
M2 [DOWN]
5
M3 [UP]
1,2/1,3+
5D
15
A
1
B
10
C
9
D
3
2
6
7
13
6,1,4
MAX/MIN
12
2(CT=0) Z6
3(CT=15) Z6
14
CLK
G4
C5
11
[1]
[2]
[4]
[8]
CTEN
D/U
LOAD
QA
QB
QC
QD
RCO
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B DECEMBER 1982 REVISED MAY 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
Pin numbers shown are for the D, J, N, and W packages.
S
C1
1D
R
7
9
S
C1
1D
R
6
10
S
C1
1D
R
2
1
S
C1
1D
R
3
15
11
14
5
4
12
13
QA
QB
QC
QD
RCO
CTEN
D/U
LOAD
MAX/MIN
CLK
A
B
C
D
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B DECEMBER 1982 REVISED MAY 1997
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
typical load, count, and inhibit sequence
The following sequence is illustrated below:
1.
Load (preset) to binary 13
2.
Count up to 14, 15 (maximum), 0, 1, and 2
3.
Inhibit
4.
Count down to 1, 0 (minimum), 15, 14, and 13
Data
Inputs
Data
Outputs
LOAD
A
B
C
D
CLK
D/U
CTEN
MAX/MIN
QA
QB
QC
QD
Load
Count Up
Inhibit
13
14
15
0
1
2
RCO
Count Down
2
2
1
0
15
14
13
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B DECEMBER 1982 REVISED MAY 1997
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
78
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54HC191
SN74HC191
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
2
5
6
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VCC = 6 V
4.2
4.2
VCC = 2 V
0
0.5
0
0.5
VIL
Low-level input voltage
VCC = 4.5 V
0
1.35
0
1.35
V
VCC = 6 V
0
1.8
0
1.8
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
0
1000
0
1000
tt
Input transition (rise and fall) time
VCC = 4.5 V
0
500
0
500
ns
VCC = 6 V
0
400
0
400
TA
Operating free-air temperature
55
125
40
85
C
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B DECEMBER 1982 REVISED MAY 1997
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HC191
SN74HC191
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
1.9
1.998
1.9
1.9
IOH = 20
A
4.5 V
4.4
4.499
4.4
4.4
VOH
VI = VIH or VIL
6 V
5.9
5.999
5.9
5.9
V
IOH = 4 mA
4.5 V
3.98
4.3
3.7
3.84
IOH = 5.2 mA
6 V
5.48
5.8
5.2
5.34
2 V
0.002
0.1
0.1
0.1
IOL = 20
A
4.5 V
0.001
0.1
0.1
0.1
VOL
VI = VIH or VIL
6 V
0.001
0.1
0.1
0.1
V
IOL = 4 mA
4.5 V
0.17
0.26
0.4
0.33
IOL = 5.2 mA
6 V
0.15
0.26
0.4
0.33
II
VI = VCC or 0
6 V
0.1
100
1000
1000
nA
ICC
VI = VCC or 0,
IO = 0
6 V
8
160
80
A
Ci
2 V to 6 V
3
10
10
10
pF
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B DECEMBER 1982 REVISED MAY 1997
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25
C
SN54HC191
SN74HC191
UNIT
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
0
4.2
0
2.8
0
3.3
fclock
Clock frequency
4.5 V
0
21
0
14
0
17
MHz
6 V
0
24
0
16
0
19
2 V
120
180
150
LOAD low
4.5 V
24
36
30
t
Pulse duration
6 V
21
31
26
ns
tw
Pulse duration
2 V
120
180
150
ns
CLK high or low
4.5 V
24
36
30
6 V
21
31
26
2 V
150
230
188
Data before LOAD
4.5 V
30
46
38
6 V
25
38
32
2 V
205
306
255
CTEN before CLK
4.5 V
41
61
51
t
Setup time
6 V
35
53
44
ns
tsu
Setup time
2 V
205
306
255
ns
D/U before CLK
4.5 V
41
61
51
6 V
35
53
44
2 V
150
225
190
LOAD inactive before CLK
4.5 V
30
45
38
6 V
25
38
32
2 V
5
5
5
Data after LOAD
4.5 V
5
5
5
6 V
5
5
5
2 V
5
5
5
th
Hold time
CTEN after CLK
4.5 V
5
5
5
ns
6 V
5
5
5
2 V
5
5
5
D/U after CLK
4.5 V
5
5
5
6 V
5
5
5
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B DECEMBER 1982 REVISED MAY 1997
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HC191
SN74HC191
UNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
4.2
8
2.8
3.3
fmax
4.5 V
21
42
14
17
MHz
6 V
24
48
16
19
2 V
130
264
396
330
LOAD
Any Q
4.5 V
40
53
79
66
6 V
33
45
67
56
Q
Q
Q
2 V
135
240
360
300
A, B, C, or D
QA, QB, QC,
or QD
4.5 V
36
48
72
60
or QD
6 V
30
41
61
51
2 V
58
120
180
150
RCO
4.5 V
17
24
36
30
6 V
14
21
31
26
2 V
107
192
288
240
CLK
Any Q
4.5 V
31
38
58
48
t d
6 V
26
32
49
41
ns
tpd
2 V
123
252
378
315
ns
MAX/MIN
4.5 V
39
50
76
63
6 V
32
43
65
54
2 V
102
228
342
285
RCO
4.5 V
29
46
68
57
D/U
6 V
24
38
59
49
D/U
2 V
86
192
288
240
MAX/MIN
4.5 V
24
38
58
48
6 V
20
32
49
41
2 V
50
132
198
165
CTEN
RCO
4.5 V
15
26
40
33
6 V
13
23
34
28
2 V
38
75
110
95
tt
Any
4.5 V
8
15
22
19
ns
6 V
6
13
19
16
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load
50
pF
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B DECEMBER 1982 REVISED MAY 1997
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%
50%
10%
10%
90%
90%
VCC
VCC
0 V
0 V
tr
tf
Reference
Input
Data
Input
50%
High-Level
Pulse
50%
VCC
0 V
50%
50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%
50%
10%
10%
90%
90%
VCC
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
50%
tPLH
tPHL
50%
50%
10%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
1 MHz, ZO = 50
, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER'S RISK.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI's publication of information regarding any third
party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright
1998, Texas Instruments Incorporated
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