SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G MARCH 1996 REVISED JULY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Wide Operating Voltage Range of 2 V to 6 V
D
Typical Switch Enable Time of 18 ns
D
Low Power Consumption, 20-
A Max I
CC
D
Low Input Current of 1
A Max
D
High Degree of Linearity
D
High On-Off Output-Voltage Ratio
D
Low Crosstalk Between Switches
D
Low On-State Impedance . . .
50-
TYP at V
CC
= 6 V
D
Individual Switch Controls
description/ordering information
The SN74HC4066 is a silicon-gate CMOS quadruple analog switch designed to handle both analog and digital
signals. Each switch permits signals with amplitudes of up to 6 V (peak) to be transmitted in either direction.
Each switch section has its own enable input control (C). A high-level voltage applied to C turns on the
associated switch section.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube of 25
SN74HC4066N
SN74HC4066N
Tube of 50
SN74HC4066D
SOIC D
Reel of 2500
SN74HC4066DR
HC4066
Reel of 250
SN74HC4066DT
40
C to 85
C
SOP NS
Reel of 2000
SN74HC4066NSR
HC4066
SSOP DB
Reel of 2000
SN74HC4066DBR
HC4066
Tube of 90
SN74HC4066PW
TSSOP PW
Reel of 2000
SN74HC4066PWR
HC4066
Reel of 250
SN74HC4066PWT
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each switch)
INPUT
CONTROL
(C)
SWITCH
L
OFF
H
ON
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
2B
2A
2C
3C
GND
V
CC
1C
4C
4A
4B
3B
3A
D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G MARCH 1996 REVISED JULY 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram, each switch (positive logic)
A
VCC
VCC
B
One of Four Switches
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control-input diode current, I
I
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O port diode current, I
I
(V
I
< 0 or V
I/O
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-state switch current (V
I/O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
96
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
76
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltages are with respect to ground unless otherwise specified.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G MARCH 1996 REVISED JULY 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
V
VI/O
I/O port voltage
0
VCC
V
VCC = 2 V
1.5
VCC
VIH
High-level input voltage, control inputs
VCC = 4.5 V
3.15
VCC
V
VCC = 6 V
4.2
VCC
VCC = 2 V
0
0.3
VIL
Low-level input voltage, control inputs
VCC = 4.5 V
0
0.9
V
VCC = 6 V
0
1.2
VCC = 2 V
1000
t/
v
Input transition rise/fall time
VCC = 4.5 V
500
ns
VCC = 6 V
400
TA
Operating free-air temperature
40
85
C
With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
TA = 25
_
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
I
1
A V
0 t V
2 V
150
ron
On-state switch resistance
IT = 1 mA, VI = 0 to VCC,
VC = VIH (see Figure 1)
4.5 V
50
85
106
VC = VIH (see Figure 1)
6 V
30
V
V
GND V
V
2 V
320
ron(p)
Peak on-state resistance
VI = VCC or GND, VC = VIH,
IT = 1 mA
4.5 V
70
170
215
( )
IT = 1 mA
6 V
50
II
Control input current
VC = 0 or VCC
6 V
0.1
100
1000
nA
Isoff
Off-state switch leakage current
VI = VCC or 0, VO = VCC or 0,
VC = VIL (see Figure 2)
6 V
0.1
5
A
Ison
On-state switch leakage current
VI = VCC or 0, VC = VIH
(see Figure 3)
6 V
0.1
5
A
ICC
Supply current
VI = 0 or VCC,
IO = 0
6 V
2
20
A
Ci
Input capacitance
A or B
5 V
9
pF
Ci
Input capacitance
C
5 V
3
10
10
pF
Cf
Feed-through
capacitance
A to B
VI = 0
0.5
pF
Co
Output capacitance
A or B
5 V
9
pF
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G MARCH 1996 REVISED JULY 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range
PARAMETER
FROM
TO
TEST
VCC
TA = 25
_
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
t
P
ti
C
50 F
2 V
10
60
75
tPLH,
tPHL
Propagation
delay time
A or B
B or A
CL = 50 pF
(see Figure 4)
4.5 V
4
12
15
ns
tPHL
delay time
(see Figure 4)
6 V
3
10
13
t
S it h
RL = 1 k
,
2 V
70
180
225
tPZH,
tPZL
Switch
turn-on time
C
A or B
RL = 1 k
,
CL = 50 pF
4.5 V
21
36
45
ns
tPZL
turn-on time
L
(see Figure 5)
6 V
18
31
38
t
S it h
RL = 1 k
,
2 V
50
200
250
tPLZ,
tPHZ
Switch
turn-off time
C
A or B
RL = 1 k
,
CL = 50 pF
4.5 V
25
40
50
ns
tPHZ
turn-off time
L
(see Figure 5)
6 V
22
34
43
Control
CL = 15 pF,
RL = 1 k
2 V
15
fI
Control
input
frequency
C
A or B
RL = 1 k
,
VC = VCC or GND,
V
V
/2
4.5 V
30
MHz
frequency
VO = VCC/2
(see Figure 6)
6 V
30
Control
feed-through
C
A or B
CL = 50 pF,
Rin = RL = 600
,
VC = VCC or GND
4.5 V
15
mV
feed-through
noise
C
A or B
VC = VCC or GND,
fin = 1 MHz
(see Figure 7)
6 V
20
(rms)
operating characteristics, V
CC
= 4.5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per gate
CL = 50 pF,
f = 1 MHz
45
pF
Minimum through bandwidth, A to B or B to A [20 log (VO/VI)] = 3 dB
CL = 50 pF,
VC = VCC
RL = 600
,
(see Figure 8)
30
MHz
Crosstalk between any switches
CL = 10 pF,
fin = 1 MHz
RL = 50
,
(see Figure 9)
45
dB
Feed through, switch off, A to B or B to A
CL = 50 pF,
fin = 1 MHz
RL = 600
,
(see Figure 10)
42
dB
Amplitude distortion rate, A to B or B to A
CL = 50 pF,
fin = 1 kHz
RL = 10 k
,
(see Figure 11)
0.05%
Adjust the input amplitude for output = 0 dBm at f = 1 MHz. Input signal must be a sine wave.
Adjust the input amplitude for input = 0 dBm at f = 1 MHz. Input signal must be a sine wave.
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G MARCH 1996 REVISED JULY 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC
VI = VCC
VC = VIH
1.0 mA
+
VO
r
on
+
V
IO
10
3
W
VIO
VCC
GND
(ON)
V
Figure 1. On-State Resistance Test Circuit
VCC
VC = VIL
A
B
VS = VA VB
CONDITION 1: VA = 0, VB = VCC
CONDITION 2: VA = VCC, VB = 0
VCC
GND
(OFF)
A
Figure 2. Off-State Switch Leakage-Current Test Circuit
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G MARCH 1996 REVISED JULY 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC
VC = VIH
A
B
Open
VCC
VA = VCC TO GND
VCC
GND
(ON)
A
Figure 3. On-State Leakage-Current Test Circuit
VCC
VC = VIH
VI
VO
50 pF
TEST CIRCUIT
tPLH
tPHL
50%
50%
VCC
0 V
50%
50%
VOH
VOL
VI
A or B
VO
B or A
VOLTAGE WAVEFORMS
50
tr
90%
10%
tf
10%
90%
VCC
GND
(ON)
Figure 4. Propagation Delay Time, Signal Input to Signal Output
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G MARCH 1996 REVISED JULY 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CL
50 pF
GND
VCC
VI
VO
TEST CIRCUIT
tPLZ
50%
VOLTAGE WAVEFORMS
RL
1 k
10%
S1
VC
50
S2
tPZH
tPHZ
50%
50%
50%
90%
tPZL
tPZH
tPLZ
tPHZ
GND
VCC
GND
VCC
TEST
S1
S2
VCC
GND
VCC
GND
tPZL
50%
VCC
VO
50%
0 V
VOL
VOH
VC
(tPZL, tPZH)
(tPLZ, tPHZ)
VCC
VCC
VO
0 V
VOL
VOH
VC
VCC
0 V
VOL
VOH
VCC
0 V
VOL
VOH
Figure 5. Switching Time (t
PZL
, t
PLZ,
t
PZH
, t
PHZ
), Control to Signal Output
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G MARCH 1996 REVISED JULY 2003
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC
GND
VO
RL
1 k
CL
15 pF
VCC
VC
50
VI = VCC
VCC
VC
0 V
VCC/2
Figure 6. Control-Input Frequency
VCC
GND
VO
RL
600
CL
50 pF
VCC
VC
50
VI
VCC/2
Rin
600
VCC/2
tr
tf
90%
10%
(f = 1 MHz)
tr = tf = 6 ns
90%
10%
VCC
VC
0 V
Figure 7. Control Feed-Through Noise
VO
VCC
50
fin
VCC/2
VC = VCC
0.1
F
VI
VI
(VI = 0 dBm at f = 1 MHz)
VCC
GND
(ON)
RL
600
CL
50 pF
Figure 8. Minimum Through Bandwidth
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G MARCH 1996 REVISED JULY 2003
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VO1
RL
600
CL
50 pF
VCC
50
fin
VCC/2
VC = VCC
0.1
F
VI
VI
(VI = 0 dBm at f = 1 MHz)
VO2
VCC
Rin
600
VCC/2
VC = GND
Rin
600
VCC
GND
(ON)
VCC
GND
(OFF)
RL
600
CL
50 pF
Figure 9. Crosstalk Between Any Two Switches
VO
VCC
50
fin
VC = GND
0.1
F
VI
VI
(VI = 0 dBm at f = 1 MHz)
VCC
GND
(OFF)
Rin
600
RL
600
CL
50 pF
VCC/2
VCC/2
Figure 10. Feed Through, Switch Off
VI
(VI = 0 dBm at f = 1 kHz)
VO
RL
10 k
CL
50 pF
VCC
VCC/2
VC = VCC
10
F
VI
fin
VCC
GND
(ON)
Figure 11. Amplitude-Distortion Rate
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
BB
AC
AD
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
Gauge Plane
0.015 (0,38)
0.430 (10,92) MAX
20
1.060
(26,92)
0.940
(23,88)
18
0.920
0.850
14
0.775
0.745
(19,69)
(18,92)
16
0.775
(19,69)
(18,92)
0.745
A MIN
DIM
A MAX
PINS **
(23,37)
(21,59)
Seating Plane
14/18 PIN ONLY
20 pin vendor option
4040049/E 12/2002
9
8
0.070 (1,78)
A
0.045 (1,14)
0.020 (0,51) MIN
16
1
0.015 (0,38)
0.021 (0,53)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.240 (6,10)
0.260 (6,60)
M
0.010 (0,25)
0.100 (2,54)
16 PINS SHOWN
MS-100
VARIATION
AA
C
D
D
D
0.030 (0,76)
0.045 (1,14)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN
(4,80)
0.189
0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1
4
8
5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0
8
Gage Plane
A
0.004 (0,10)
0.010 (0,25)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,90
7,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
20
16
6,50
6,50
14
0,05 MIN
5,90
5,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65
M
0,15
0
8
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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