SN54HCT573, SN74HCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS176E MARCH 1984 REVISED JULY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Operating Voltage Range of 4.5 V to 5.5 V
D
High-Current 3-State Outputs Drive Bus
Lines Directly or Up To 15 LSTTL Loads
D
Low Power Consumption, 80-
A Max I
CC
D
Typical t
pd
= 21 ns
D
6-mA Output Drive at 5 V
D
Low Input Current of 1
A Max
D
Inputs Are TTL-Voltage Compatible
D
Bus-Structured Pinout
description/ordering information
These octal transparent D-type latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. The 'HCT573 devices are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
While the latch-enable (LE) input is high, the
Q outputs respond to the data (D) inputs. When
LE is low, the outputs are latched to retain the data
that was set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased
drive provide the capability to drive bus lines without interface or pullup components.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74HCT573N
SN74HCT573N
SOIC
DW
Tube
SN74HCT573DW
HCT573
SOIC DW
Tape and reel
SN74HCT573DWR
HCT573
40
C to 85
C
SOP NS
Tape and reel
SN74HCT573NSR
HCT573
SSOP DB
Tape and reel
SN74HCT573DBR
HT573
TSSOP
PW
Tube
SN74HCT573PW
HT573
TSSOP PW
Tape and reel
SN74HCT573PWR
HT573
CDIP J
Tube
SNJ54HCT573J
SNJ54HCT573J
55
C to 125
C
CFP W
Tube
SNJ54HCT573W
SNJ54HCT573W
LCCC FK
Tube
SNJ54HCT573FK
SNJ54HCT573FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q
V
1Q
8D
GND
LE
SN54HCT573 . . . FK PACKAGE
(TOP VIEW)
CC
SN54HCT573 . . . J OR W PACKAGE
SN74HCT573 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
Copyright
2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
SN54HCT573, SN74HCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS176E MARCH 1984 REVISED JULY 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
LE
1D
1Q
1
11
2
19
To Seven Other Channels
C1
1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
35 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
70 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
69
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
60
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
83
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54HCT573, SN74HCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS176E MARCH 1984 REVISED JULY 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HCT573
SN74HCT573
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
2
2
V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
t/
v
Input transition rise/fall time
500
500
ns
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HCT573
SN74HCT573
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VOH
VI = VIH or VIL
IOH = 20
A
4 5 V
4.4
4.499
4.4
4.4
V
VOH
VI = VIH or VIL
IOH = 6 mA
4.5 V
3.98
4.3
3.7
3.84
V
VOL
VI = VIH or VIL
IOL = 20
A
4 5 V
0.001
0.1
0.1
0.1
V
VOL
VI = VIH or VIL
IOL = 6 mA
4.5 V
0.17
0.26
0.4
0.33
V
II
VI = VCC or 0
5.5 V
0.1
100
1000
1000
nA
IOZ
VO = VCC or 0
5.5 V
0.01
0.5
10
5
A
ICC
VI = VCC or 0,
IO = 0
5.5 V
8
160
80
A
ICC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
5.5 V
1.4
2.4
3
2.9
mA
Ci
4.5 V
to 5.5 V
3
10
10
10
pF
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25
C
SN54HCT573
SN74HCT573
UNIT
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration LE high
4.5 V
20
30
25
ns
tw
Pulse duration, LE high
5.5 V
17
27
23
ns
t
Setup time data before LE
4.5 V
10
15
13
ns
tsu
Setup time, data before LE
5.5 V
9
14
12
ns
th
Hold time data after LE
4.5 V
5
5
5
ns
th
Hold time, data after LE
5.5 V
5
5
5
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54HCT573, SN74HCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS176E MARCH 1984 REVISED JULY 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HCT573
SN74HCT573
UNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
D
Q
4.5 V
25
35
53
44
t d
D
Q
5.5 V
21
32
48
40
ns
tpd
LE
Any Q
4.5 V
28
35
53
44
ns
LE
Any Q
5.5 V
25
32
48
40
t
OE
Any Q
4.5 V
26
35
53
44
ns
ten
OE
Any Q
5.5 V
23
32
48
40
ns
tdi
OE
Any Q
4.5 V
23
35
53
44
ns
tdis
OE
Any Q
5.5 V
22
32
48
40
ns
tt
Any Q
4.5 V
9
12
18
15
ns
tt
Any Q
5.5 V
9
11
16
14
ns
switching characteristics over recommended operating free-air temperature range, C
L
= 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HCT573
SN74HCT573
UNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
D
Q
4.5 V
32
52
79
65
t d
D
Q
5.5 V
27
47
71
59
ns
tpd
LE
Any Q
4.5 V
38
52
79
65
ns
LE
Any Q
5.5 V
36
47
71
59
t
OE
Any Q
4.5 V
33
52
79
65
ns
ten
OE
Any Q
5.5 V
28
47
71
59
ns
tt
Any Q
4.5 V
18
42
63
53
ns
tt
Any Q
5.5 V
16
38
57
48
ns
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per latch
No load
50
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54HCT573, SN74HCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS176E MARCH 1984 REVISED JULY 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
1.3 V
1.3 V
1.3 V
0.3 V
0.3 V
2.7 V
2.7 V
3 V
3 V
0 V
0 V
tr
tf
Reference
Input
Data
Input
1.3 V
High-Level
Pulse
1.3 V
3 V
0 V
1.3 V
1.3 V
3 V
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
1.3 V
1.3 V
10%
10%
90%
90%
3 V
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
1.3 V
tPLH
tPHL
1.3 V
1.3 V
10%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-
Phase
Output
1.3 V
10%
90%
3 V
VCC
VOL
0 V
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
1.3 V
tPZL
tPLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOH
0 V
1.3 V
1.3 V
tPZH
tPHZ
Output
Waveform 2
(See Note B)
Test
Point
From Output
Under Test
RL
VCC
S1
S2
LOAD CIRCUIT
PARAMETER
CL
tPZH
tpd or tt
tdis
ten
tPZL
tPHZ
tPLZ
1 k
1 k
50 pF
or
150 pF
50 pF
Open
Closed
RL
S1
Closed
Open
S2
Open
Closed
Closed
Open
50 pF
or
150 pF
Open
Open
CL
(see Note A)
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
1 MHz, ZO = 50
, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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