SN54LV244A, SN74LV244A
OCTAL BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCLS383L - SEPTEMBER 1997 - REVISED APRIL 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
2-V to 5.5-V V
CC
Operation
D
Max t
pd
of 6.5 ns at 5 V
D
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
C
D
Typical V
OHV
(Output V
OH
Undershoot)
>2.3 V at V
CC
= 3.3 V, T
A
= 25
C
D
Support Mixed-Mode Voltage Operation on
All Ports
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
SN54LV244A . . . J OR W PACKAGE
SN74LV244A . . . DB, DGV, DW, NS
OR PW PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
SN54LV244A . . . FK PACKAGE
(TOP VIEW)
2Y4
1A1
1OE
1Y4
2A2
2OE
2Y1
GND
2A1
V
CC
SN74LV244A . . . RGY PACKAGE
(TOP VIEW)
1
20
10
11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
1OE
2A1
V
GND
CC
description/ordering information
These octal buffers/line drivers are designed for 2-V to 5.5-V V
CC
operation.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN - RGY
Reel of 1000
SN74LV244ARGYR
LV244A
SOIC - DW
Tube of 25
SN74LV244ADW
LV244A
SOIC - DW
Reel of 2000
SN74LV244ADWR
LV244A
SOP - NS
Reel of 2000
SN74LV244ANSR
74LV244A
-40
C to 85
C
SSOP - DB
Reel of 2000
SN74LV244ADBR
LV244A
-40 C to 85 C
Tube of 70
SN74LV244APW
TSSOP - PW
Reel of 2000
SN74LV244APWR
LV244A
TSSOP - PW
Reel of 250
SN74LV244APWT
LV244A
TVSOP - DGV
Reel of 2000
SN74LV244ADGVR
LV244A
CDIP - J
Tube of 20
SNJ54LV244AJ
SNJ54LV244AJ
-55
C to 125
C
CFP - W
Tube of 85
SNJ54LV244AW
SNJ54LV244AW
-55 C to 125 C
LCCC - FK
Tube of 55
SNJ54LV244AFK
SNJ54LV244AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2005, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV244A, SN74LV244A
OCTAL BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCLS383L - SEPTEMBER 1997 - REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The 'LV244A devices are designed specifically to improve both the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low,
the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
logic diagram (positive logic)
1
2
18
1Y1
1OE
1A1
4
16
1Y2
1A2
6
14
1Y3
1A3
8
12
1Y4
1A4
19
11
9
2Y1
2OE
2A1
13
7
2Y2
2A2
15
5
2Y3
2A3
17
3
2Y4
2A4
SN54LV244A, SN74LV244A
OCTAL BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCLS383L - SEPTEMBER 1997 - REVISED APRIL 2005
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or
power-off state, V
O
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range applied in the high or low state, V
O
(see Notes 1 and 2)
-0.5 V to V
CC
+ 0.5 V
. . . . . .
Input clamp current, I
IK
(V
I
< 0)
-20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
35 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
70 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DB package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DGV package
92
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): NS package
60
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): PW package
83
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 4): RGY package
37
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
SN54LV244A, SN74LV244A
OCTAL BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCLS383L - SEPTEMBER 1997 - REVISED APRIL 2005
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 5)
SN54LV244A
SN74LV244A
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2
5.5
2
5.5
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC
0.7
VCC
0.7
V
VIH
High-level input voltage
VCC = 3 V to 3.6 V
VCC
0.7
VCC
0.7
V
VCC = 4.5 V to 5.5 V
VCC
0.7
VCC
0.7
VCC = 2 V
0.5
0.5
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
VCC
0.3
VCC
0.3
V
VIL
Low-level input voltage
VCC = 3 V to 3.6 V
VCC
0.3
VCC
0.3
V
VCC = 4.5 V to 5.5 V
VCC
0.3
VCC
0.3
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
High or low state
0
VCC
0
VCC
V
VO
Output voltage
3-state
0
5.5
0
5.5
V
VCC = 2 V
-50
-50
A
IOH
High-level output current
VCC = 2.3 V to 2.7 V
-2
-2
IOH
High-level output current
VCC = 3 V to 3.6 V
-8
-8
mA
VCC = 4.5 V to 5.5 V
-16
-16
mA
VCC = 2 V
50
50
A
IOL
Low-level output current
VCC = 2.3 V to 2.7 V
2
2
IOL
Low-level output current
VCC = 3 V to 3.6 V
8
8
mA
VCC = 4.5 V to 5.5 V
16
16
mA
VCC = 2.3 V to 2.7 V
200
200
t/
v
Input transition rise or fall rate
VCC = 3 V to 3.6 V
100
100
ns/V
t/
v
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V
20
20
ns/V
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV244A, SN74LV244A
OCTAL BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCLS383L - SEPTEMBER 1997 - REVISED APRIL 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
SN54LV244A
SN74LV244A
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
IOH = -50
A
2 V to 5.5 V
VCC-0.1
VCC-0.1
VOH
IOH = -2 mA
2.3 V
2
2
V
VOH
IOH = -8 mA
3 V
2.48
2.48
V
IOH = -16 mA
4.5 V
3.8
3.8
IOL = 50
A
2 V to 5.5 V
0.1
0.1
VOL
IOL = 2 mA
2.3 V
0.4
0.4
V
VOL
IOL = 8 mA
3 V
0.44
0.44
V
IOL = 16 mA
4.5 V
0.55
0.55
II
VI = 5.5 V or GND
0 to 5.5 V
1
1
A
IOZ
VO = VCC or GND
5.5 V
5
5
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
20
20
A
Ioff
VI or VO = 0 to 5.5 V
0
5
5
A
Ci
VI = VCC or GND
3.3 V
2.3
2.3
pF
switching characteristics over recommended operating free-air temperature range,
V
CC
= 2.5 V
0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
SN54LV244A
SN74LV244A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tpd
A
Y
7.5*
12.5*
1*
15*
1
15
ten
OE
Y
CL = 15 pF
8.9*
14.6*
1*
17*
1
17
ns
tdis
OE
Y
CL = 15 pF
9.1*
14.1*
1*
16*
1
16
ns
tpd
A
Y
9.5
15.3
1
18
1
18
ten
OE
Y
CL = 50 pF
10.8
17.8
1
21
1
21
ns
tdis
OE
Y
CL = 50 pF
13.4
19.2
1
21
1
21
ns
tsk(o)
2
2
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
SN54LV244A
SN74LV244A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tpd
A
Y
5.4*
8.4*
1*
10*
1
10
ten
OE
Y
CL = 15 pF
6.3*
10.6*
1*
12.5*
1
12.5
ns
tdis
OE
Y
CL = 15 pF
7.6*
11.7*
1*
13*
1
13
ns
tpd
A
Y
6.8
11.9
1
13.5
1
13.5
ten
OE
Y
CL = 50 pF
7.8
14.1
1
16
1
16
ns
tdis
OE
Y
CL = 50 pF
11
16
1
18
1
18
ns
tsk(o)
1.5
1.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV244A, SN74LV244A
OCTAL BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCLS383L - SEPTEMBER 1997 - REVISED APRIL 2005
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
SN54LV244A
SN74LV244A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tpd
A
Y
3.9*
5.5*
1*
6.5*
1
6.5
ten
OE
Y
CL = 15 pF
4.5*
7.3*
1*
8.5*
1
8.5
ns
tdis
OE
Y
CL = 15 pF
6.5*
12.2*
1*
13.5*
1
13.5
ns
tpd
A
Y
4.9
7.5
1
8.5
1
8.5
ten
OE
Y
CL = 50 pF
5.6
9.3
1
10.5
1
10.5
ns
tdis
OE
Y
CL = 50 pF
8.8
14.2
1
15.5
1
15.5
ns
tsk(o)
1
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
CC
= 3.3 V, C
L
= 50 pF, T
A
= 25
C (see Note 6
)
PARAMETER
SN74LV244A
UNIT
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.55
V
VOL(V)
Quiet output, minimum dynamic VOL
-0.5
V
VOH(V)
Quiet output, minimum dynamic VOH
2.9
V
VIH(D)
High-level dynamic input voltage
2.31
V
VIL(D)
Low-level dynamic input voltage
0.99
V
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
VCC
TYP
UNIT
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
3.3 V
14
pF
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
5 V
16
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV244A, SN74LV244A
OCTAL BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCLS383L - SEPTEMBER 1997 - REVISED APRIL 2005
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
50% VCC
VOL
+ 0.3 V
50% VCC
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST
S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr
3 ns, tf
3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL = 1 k
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
VOH -
0.3 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
SN74LV244ADBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
SN74LV244ADBR
ACTIVE
SSOP
DB
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LV244ADBRE4
ACTIVE
SSOP
DB
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LV244ADGVR
ACTIVE
TVSOP
DGV
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV244ADGVRE4
ACTIVE
TVSOP
DGV
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV244ADW
ACTIVE
SOIC
DW
20
25
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74LV244ADWE4
ACTIVE
SOIC
DW
20
25
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74LV244ADWR
ACTIVE
SOIC
DW
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74LV244ANSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV244ANSRE4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV244ANSRG4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV244APW
ACTIVE
TSSOP
PW
20
70
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV244APWE4
ACTIVE
TSSOP
PW
20
70
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV244APWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV244APWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
SN74LV244APWR
ACTIVE
TSSOP
PW
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV244APWRE4
ACTIVE
TSSOP
PW
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV244APWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV244APWT
ACTIVE
TSSOP
PW
20
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV244APWTE4
ACTIVE
TSSOP
PW
20
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV244ARGYR
ACTIVE
QFN
RGY
20
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jul-2005
Addendum-Page 1
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jul-2005
Addendum-Page 2
MECHANICAL DATA
MPDS006C FEBRUARY 1996 REVISED AUGUST 2000
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50
4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
1
12
24
13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
38
24
16
4,90
5,10
3,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins MO-153
14/16/20/56 Pins MO-194
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,90
7,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
20
16
6,50
6,50
14
0,05 MIN
5,90
5,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65
M
0,15
0
8
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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solutions:
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Applications
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amplifier.ti.com
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www.ti.com/audio
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dataconverter.ti.com
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www.ti.com/automotive
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dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
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www.ti.com/security
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www.ti.com/telephony
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www.ti.com/video
Wireless
www.ti.com/wireless
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Copyright
2005, Texas Instruments Incorporated
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