SN74LVC2GU04
DUAL INVERTER GATE
SCES197J APRIL 1999 REVISED FEBRUARY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Available in the Texas Instruments
NanoStar
and NanoFree
Packages
D
Supports 5-V V
CC
Operation
D
Inputs Accept Voltages to 5.5 V
D
Max t
pd
of 3.7 ns at 3.3 V
D
Low Power Consumption, 10-
A Max I
CC
D
24-mA Output Drive at 3.3 V
D
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
C
D
Typical V
OHV
(Output V
OH
Undershoot)
>2 V at V
CC
= 3.3 V, T
A
= 25
C
D
Unbuffered Outputs
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
description/ordering information
This dual inverter is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC2GU04 contains two inverters with unbuffered outputs and performs the Boolean function Y = A.
NanoStar
and NanoFree
package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
NanoStar
WCSP (DSBGA)
0.17-mm Small Bump YEA
SN74LVC2GU04YEAR
NanoFree
WCSP (DSBGA)
0.17-mm Small Bump YZA (Pb-free)
Reel of 3000
SN74LVC2GU04YZAR
CD
NanoStar
WCSP (DSBGA)
0.23-mm Large Bump YEP
Reel of 3000
SN74LVC2GU04YEPR
_ _ _CD_
40
C to 85
C
NanoFree
WCSP (DSBGA)
0.23-mm Large Bump YZP (Pb-free)
SN74LVC2GU04YZPR
SOT (SOT 23)
DBV
Reel of 3000
SN74LVC2GU04DBVR
CU4
SOT (SOT-23) DBV
Reel of 250
SN74LVC2GU04DBVT
CU4_
SOT (SC 70)
DCK
Reel of 3000
SN74LVC2GU04DCKR
CD
SOT (SC-70) DCK
Reel of 3000
SN74LVC2GU04DCKT
CD_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site.
Copyright
2003, Texas Instruments Incorporated
NanoStar and NanoFree are trademarks of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
6
5
4
1A
GND
2A
1Y
V
CC
2Y
3
2
1
4
5
6
2A
GND
1A
2Y
V
CC
1Y
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74LVC2GU04
DUAL INVERTER GATE
SCES197J APRIL 1999 REVISED FEBRUARY 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram (positive logic)
1A
1Y
1
6
2A
2Y
3
4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DBV package
165
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package
259
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YEA/YZA package
143
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . .
YEP/YZP package
123
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74LVC2GU04
DUAL INVERTER GATE
SCES197J APRIL 1999 REVISED FEBRUARY 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
VCC
Supply voltage
1.65
5.5
V
VIH
High-level input voltage
IO = 100
m
A
0.75
VCC
V
VIL
Low-level input voltage
IO = 100
m
A
0.25
VCC
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
4
VCC = 2.3 V
8
IOH
High-level output current
VCC = 3 V
16
mA
VCC = 3 V
24
VCC = 4.5 V
32
VCC = 1.65 V
4
VCC = 2.3 V
8
IOL
Low-level output current
VCC = 3 V
16
mA
VCC = 3 V
24
VCC = 4.5 V
32
TA
Operating free-air temperature
40
85
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
IOH = 100
m
A
1.65 V to 5.5 V
VCC0.1
IOH = 4 mA
1.65 V
1.2
VOH
VIL = 0 V
IOH = 8 mA
2.3 V
1.9
V
VOH
VIL = 0 V
IOH = 16 mA
3 V
2.4
V
IOH = 24 mA
3 V
2.3
IOH = 32 mA
4.5 V
3.8
IOL = 100
m
A
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
VOL
VIH= VCC
IOL = 8 mA
2.3 V
0.3
V
VOL
VIH= VCC
IOL = 16 mA
3 V
0.4
V
IOL = 24 mA
3 V
0.55
IOL = 32 mA
4.5 V
0.55
II
A inputs
VI = 5.5 V or GND
0 to 5.5 V
5
m
A
ICC
VI = 5.5 V or GND,
IO = 0
1.65 V to 5.5 V
10
m
A
Ci
VI = VCC or GND
3.3 V
7
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
0.15 V
VCC = 2.5 V
0.2 V
VCC = 3.3 V
0.3 V
VCC = 5 V
0.5 V
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tpd
A
Y
1.2
5.5
1
4
1.1
3.7
1
3
ns
SN74LVC2GU04
DUAL INVERTER GATE
SCES197J APRIL 1999 REVISED FEBRUARY 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
VCC = 5 V
UNIT
PARAMETER
TEST CONDITIONS
TYP
TYP
TYP
TYP
UNIT
Cpd
Power dissipation capacitance
f = 10 MHz
7
7
8
23
pF
SN74LVC2GU04
DUAL INVERTER GATE
SCES197J APRIL 1999 REVISED FEBRUARY 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
VLOAD
Open
GND
RL
RL
Data Input
Timing Input
VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V
VOH V
0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VM
VM
VM
VM
VM
VM
VM
VM
VM
VM
VM
VM
VI
VM
VM
1.8 V
0.15 V
2.5 V
0.2 V
3.3 V
0.3 V
5 V
0.5 V
1 k
500
500
500
VCC
RL
2
VCC
2
VCC
6 V
2
VCC
VLOAD
CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
2 ns
2 ns
2.5 ns
2.5 ns
INPUTS
Figure 1. Load Circuit and Voltage Waveforms
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