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SN54F299, SN74F299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDFS071A MARCH 1987 REVISED OCTOBER 1993
Copyright
1993, Texas Instruments Incorporated
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Four Modes of Operation:
Hold (Store)
Shift Right
Shift Left
Load Data
Operates With Outputs Enabled or at High
Impedance
3-State Outputs Drive Bus Lines Directly
Can Be Cascaded for N-Bit Word Lengths
Direct Overriding Clear
Applications:
Stacked or Push-Down Registers
Buffer Storage
Accumulator Registers
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These 8-bit universal shift /storage registers
feature multiplexed I/O ports to achieve full 8-bit
data handling in a single 20-pin package. Two
function-select (S0, S1) inputs and two
output-enable (OE1, OE2) inputs can be used to
choose the modes of operation listed in the
function table.
Synchronous parallel loading is accomplished by
taking both S0 and S1 high. This places the 3-state
outputs in a high-impedance state and permits
data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be
accomplished while the outputs are enabled in any mode. Clearing occurs when the clear (CLR) input is low.
Taking either OE1 or OE2 high disables the outputs but has no effect on clearing, shifting, or storage of data.
The SN54F299 is characterized for operation over the full military temperature range of 55
C to 125
C. The
SN74F299 is characterized for operation from 0
C to 70
C.
SN54F299 . . . J PACKAGE
SN74F299 . . . DW OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
SL
Q
H
H/Q
H
F/Q
F
D/Q
D
G/Q
G
E/Q
E
C/Q
C
A/Q
A
Q
A
SN54F299 . . . FK PACKAGE
(TOP VIEW)
OE2
OE1
S0
CLK
B
S1
CLR
GND
SR
V
CC
B/Q
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
S0
OE1
OE2
G/Q
G
E/Q
E
C/Q
C
A/Q
A
Q
A
CLR
GND
V
CC
S1
SL
Q
H
H/Q
H
F/Q
F
D/Q
D
B/Q
B
CLK
SR
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54F299, SN74F299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDFS071A MARCH 1987 REVISED OCTOBER 1993
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
MODE
INPUTS
I/O PORTS
OUTPUTS
MODE
CLR
S1
S0
OE1
OE2
CLK
SL
SR
A/QA B/QB C/QC D/QD E/QE
F/QF G/QG H/QH
QA
QH
Clear
L
L
L
X
L
H
L
X
H
L
L
X
L
L
X
X
X
X
X
X
X
X
X
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
L
L
L
L
Hold
H
H
L
X
L
X
L
L
L
L
X
L
X
X
X
X
QA0
QA0
QB0
QB0
QC0
QC0
QD0
QD0
QE0
QE0
QF0
QF0
QG0
QG0
QH0
QH0
QA0
QA0
QH0
QH0
Shift
Right
H
H
L
L
H
H
L
L
L
L
X
X
H
L
H
L
QAn
QAn
QBn
QBn
QCn
QCn
QDn
QDn
QEn
QEn
QFn
QFn
QGn
QGn
H
L
QGn
QGn
Shift
Left
H
H
H
H
L
L
L
L
L
L
H
L
X
X
QBn
QBn
QCn
QCn
QDn
QDn
QEn
QEn
QFn
QFn
QGn
QGn
QHn
QHn
H
L
QBn
QBn
H
L
Load
H
H
H
X
X
X
X
a
b
c
d
e
f
g
h
a
h
NOTE: a . . . h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputs
are isolated from the I/O terminals.
When one or both output-enable inputs are high the eight I/O terminals are disabled to the high-impedance state; however, sequential operation
or clearing of the register is not affected.
logic symbol
SRG8
M
0
3
R
9
6
14
5
15
4
8
2
3
0
1
S0
1
19
S1
12
CLK
5
1,4D
11
SR
3,4D
7
5
3,4D
13
17
5
2,4D
18
SL
3,4D
16
&
3EN5
C4/1
/2
QA
QH
CLR
OE1
OE2
A /QA
H/QH
B/QB
C/QC
D/QD
E/QE
F/QF
G/QG
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54F299, SN74F299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDFS071A MARCH 1987 REVISED OCTOBER 1993
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
C1
1D
C1
1D
Six
Identical
Channels
Not
Shown
19
11
12
8
2
3
18
17
S0
S1
SR
(shift right
serial input)
CLK
QA
OE1
OE2
SL
(shift left
serial input)
QH
7
16
A /QA
H /QH
9
CLR
1
R
R
I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4).
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
1.2 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range
30 mA to 5 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state
0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state
0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state: Q
A
or Q
H
40 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN54F299 (Q
A
thru Q
H
)
40 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74F299 (Q
A
thru Q
H
)
48 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range:
SN54F299
55
C to 125
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74F299
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
SN54F299, SN74F299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDFS071A MARCH 1987 REVISED OCTOBER 1993
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
SN54F299
SN74F299
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IIK
Input clamp current
18
18
mA
IOH
High level output current
QA
or QH
1
1
mA
IOH
High-level output current
QA thru QH
3
3
mA
IOL
Low level output current
QA
or QH
20
20
mA
IOL
Low-level output current
QA thru QH
20
24
mA
TA
Operating free-air temperature
55
125
0
70
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54F299
SN74F299
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
V
QA
or QH
IOH = 1 mA
2.5
3.4
2.5
3.4
VOH
QA thru QH
VCC = 4.5 V
IOH = 1 mA
2.5
3.4
2.5
3.4
V
VOH
QA thru QH
IOH = 3 mA
2.4
3.3
2.4
3.3
V
Any output
VCC = 4.75 V,
IOH = 1 mA to 3 mA
2.7
QA
or QH
IOL = 20 mA
0.3
0.5
0.3
0.5
VOL
QA thru QH
VCC = 4.5 V
IOL = 20 mA
0.3
0.5
V
QA thru QH
IOL = 24 mA
0.35
0.5
II
A thru H
VCC = 5 5 V
VI = 5.5 V
1
1
mA
II
Any other
VCC = 5.5 V
VI = 7 V
0.1
0.1
mA
IIH
A thru H
VCC = 5 5 V
VI = 2 7 V
70
70
A
IIH
Any other
VCC = 5.5 V,
VI = 2.7 V
20
20
A
A thru H
0.65
0.65
IIL
S0 or S1
VCC = 5.5 V,
VI = 0.5 V
1.2
1.2
mA
IL
Any other
0.6
0.6
IOS
VCC = 5.5 V,
VO = 0
60
150
60
150
mA
ICC
VCC = 5.5 V,
See Note 2
68
95
68
95
mA
All typical values are at VCC = 5 V, TA = 25
C.
For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2: ICC is measured with OE1, OE2, and CLK at 4.5 V.
SN54F299, SN74F299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDFS071A MARCH 1987 REVISED OCTOBER 1993
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25
C
SN54F299
SN74F299
UNIT
F299
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
0
70
0
65
0
70
MHz
t
Pulse duration
CLK high or low
7
8
7
ns
tw
Pulse duration
CLR low
7
8
7
ns
Setup time before
S0 or S1
High or low
8.5
9.5
8.5
tsu
Setu time before
CLK
A/QA thru H/QH, SR, or SL
High or low
5.5
6.5
5.5
ns
tsu
Inactive-state setup
time before CLK
CLR
High
7
13
7
ns
th
Hold time after CLK
S0 or S1
High or low
0
0
0
ns
th
Hold time after CLK
A /QA thru H /QH, SR, or SL High or low
2
2
2
ns
Inactive-state setup time is also referred to as recovery time.
switching characteristics (see Note 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
RL = 500
,
TA = 25
C
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX
UNIT
(INPUT)
(OUTPUT)
F299
SN54F299
SN74F299
MIN
TYP
MAX
MIN
MAX
MIN
MAX
fmax
70
100
65
70
MHz
tPLH
CLK
Q
or Q
3.2
6.6
9
2.7
10.5
3.2
10
ns
tPHL
CLK
QA
or QH
2.7
6.1
8.5
2.2
10
2.7
9.5
ns
tPLH
CLK
Q
thru Q
3.2
6.6
9
2.7
11
3.2
10
ns
tPHL
CLK
QA thru QH
4.2
8.1
11
3.7
12.5
4.2
12
ns
tPHL
CLR
QA
or QH
3.7
7.1
9.5
3.2
11.5
3.7
10.5
ns
tPHL
CLR
QA thru QH
5.7
10.6
14
5
15.5
5.7
15
ns
tPZH
OE1 or OE2
Q
thru Q
2.7
5.6
8
2.2
10.5
2.7
9
ns
tPZL
OE1 or OE2
QA thru QH
3.2
6.6
10
2.7
12
3.2
11
ns
tPHZ
OE1 or OE2
QA thru QH
1.7
4.1
6
1.7
9
1.7
7
ns
tPLZ
OE1 or OE2
QA thru QH
1.2
3.6
5.5
1.2
7.5
1.2
6.5
ns
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
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