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Электронный компонент: SNJ54CBT3383W

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54CBT3383, SN74CBT3383
10-BIT FET BUS-EXCHANGE SWITCHES
SCDS003M NOVEMBER 1992 REVISED NOVEMBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
5-
Switch Connection Between Two Ports
D
TTL-Compatible Input Levels
description
The 'CBT3383 devices provide ten bits of
high-speed TTL-compatible bus switching or
exchanging. The low on-state resistance of the
switch allows connections to be made with
minimal propagation delay.
The devices operate as a 10-bit bus switch or a
5-bit bus exchanger, which provides swapping of
the A and B pairs of signals. The bus-exchange
function is selected when BX is high. The switches
are connected when BE is low.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC
DW
Tube
SN74CBT3383DW
CBT3383
SOIC DW
Tape and reel
SN74CBT3383DWR
CBT3383
40
C to 85
C
SSOP DB
Tape and reel
SN74CBT3383DBR
CU383
40
C to 85
C
SSOP (QSOP) DBQ
Tape and reel
SN74CBT3383DBQR
CBT3383
TSSOP PW
Tape and reel
SN74CBT3833PWR
CU383
TVSOP DGV
Tape and reel
SN74CBT3833DGVR
CU383
55
C to 125
C
CDIP JT
Tube
SNJ54CBT3383JT
SNJ54CBT3383JT
55
C to 125
C
CFP W
Tube
SNJ54CBT3383W
SNJ54CBT3383W
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
BE
BX
1A15A1
1A25A2
L
L
1B15B1
1B25B2
L
H
1B25B2
1B15B1
H
X
Z
Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2001, Texas Instruments Incorporated
SN54CBT3383 . . . JT OR W PACKAGE
SN74CBT3383 . . . DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
BE
1B1
1A1
1A2
1B2
2B1
2A1
2A2
2B2
3B1
3A1
GND
V
CC
5B2
5A2
5A1
5B1
4B2
4A2
4A1
4B1
3B2
3A2
BX
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54CBT3383, SN74CBT3383
10-BIT FET BUS-EXCHANGE SWITCHES
SCDS003M NOVEMBER 1992 REVISED NOVEMBER 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
3
4
2
5
1A1
1A2
1B1
1B2
21
22
20
23
5A1
5A2
5B1
5B2
BE
1
BX
13
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I/O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
63
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DBQ package
61
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
46
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
88
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54CBT3383, SN74CBT3383
10-BIT FET BUS-EXCHANGE SWITCHES
SCDS003M NOVEMBER 1992 REVISED NOVEMBER 2001
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54CBT3383
SN74CBT3383
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level control input voltage
2
2
V
VIL
Low-level control input voltage
0.8
0.8
V
TA
Operating free-air temperature
55
125
0
70
C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54CBT3383
SN74CBT3383
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
V
II
VCC = 5.5 V,
VI = 5.5 V or GND
5
1
A
ICC
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
50
50
A
ICC
Control inputs
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
2.5
2.5
mA
Ci
Control inputs
VI = 3 V or 0
3
pF
Ci
Control inputs
VI = 2.5 V
5
pF
Ci (OFF)
VO = 3 V or 0,
BE = VCC
6
pF
Cio(OFF)
VO = 2.5 V,
BE = VCC
6
pF
VI = 0
II = 64 mA
5
9.2
5
7
ron
VCC = 4.5 V
VI = 0
II = 30 mA
5
7
VI = 2.4 V,
II = 15 mA
10
17
10
15
All typical values are at VCC = 5 V, TA = 25
C.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Measured by the voltage drop between the input terminal and the output terminal at the indicated current through the switch. On-state resistance
is determined by the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
SN54CBT3383
SN74CBT3383
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
tpd
A or B
B or A
1.5
0.25
ns
tpd
BX
A or B
1
10.2
1
9.2
ns
ten
BE
A or B
1
10.8
1
8.6
ns
tdis
BE
A or B
1
8.2
1
7.5
ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
SN54CBT3383, SN74CBT3383
10-BIT FET BUS-EXCHANGE SWITCHES
SCDS003M NOVEMBER 1992 REVISED NOVEMBER 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOH
VOL
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500
500
tPLH
tPHL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH 0.3 V
0 V
Input
3 V
3.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright
2001, Texas Instruments Incorporated