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Электронный компонент: THS1040

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THS1040
SLAS290C - OCTOBER 2001 - REVISED OCTOBER 2004
3 V, 10 Bit, 40 MSPS
CMOS ANALOG TO DIGITAL CONVERTER
1
www.ti.com
FEATURES
D
Analog Supply 3 V
D
Digital Supply 3 V
D
Configurable Input Functions:
- Single Ended
- Differential
D
Differential Nonlinearity:
0.45 LSB
D
Signal-to-Noise: 60 dB Typ f
(IN)
at 4.8 MHz
D
Spurious Free Dynamic Range: 72 dB
D
Adjustable Internal Voltage Reference
D
On-Chip Voltage Reference Generator
D
Unsigned Binary Data Output
D
Out-of-Range Indicator
D
Power-Down Mode
APPLICATIONS
D
Video/CCD Imaging
D
Communications
D
Set-Top Box
D
Medical
DESCRIPTION
The THS1040 is a CMOS, low power, 10-bit, 40-MSPS
analog-to-digital converter (ADC) that operates from a
single 3-V supply. The THS1040 has been designed to
give circuit developers flexibility. The analog input to the
THS1040 can be either single-ended or differential. The
THS1040 provides a wide selection of voltage
references to match the user's design requirements.
For more design flexibility, the internal reference can be
bypassed to use an external reference to suit the dc
accuracy and temperature drift requirements of the
application. The out-of-range output indicates any
out-of-range condition in THS1040's input signal.
The speed, resolution, and single-supply operation of
the THS1040 are suited to applications in set-top-box
(STB), video, multimedia, imaging, high-speed
acquisition, and communications. The speed and
resolution ideally suit charge-couple device (CCD) input
systems such as color scanners, digital copiers, digital
cameras, and camcorders. A wide input voltage range
allows the THS1040 to be applied in both imaging and
communications systems.
The THS1040C is characterized for operation from 0
C
to 70
C, while the THS1040I is characterized for
operation from -40
C to 85
C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2001 - 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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2
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5
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7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
DV
DD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OVR
DGND
AV
DD
AIN+
VREF
AIN-
REFB
MODE
REFT
BIASREF
TEST
AGND
REFSENSE
STBY
OE
CLK
28-PIN TSSOP/SOIC PACKAGE
(TOP VIEW)
THS1040
SLAS290C - OCTOBER 2001 - REVISED OCTOBER 2004
2
www.ti.com
AVAILABLE OPTIONS
PRODUCT
PACKAGE
LEAD
PACKAGE
DESGIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKINGS
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
THS1040C
0
C to 70
C
TH1040
THS1040CPW
Tube, 50
THS1040C
TSSOP-28
PW
0
C to 70
C
TH1040
THS1040CPWR
Tube and Reel, 2000
THS1040I
TSSOP-28
PW
-40
C to 85
C
TJ1040
THS1040IPW
Tube, 50
THS1040I
-40
C to 85
C
TJ1040
THS1040IPWR
Tube and Reel, 2000
THS1040C
0
C to 70
C
TH1040
THS1040CDW
Tube, 20
THS1040C
SOP-28
DW
0
C to 70
C
TH1040
THS1040CDWR
Tube and Reel, 1000
THS1040I
SOP-28
DW
-40
C to 85
C
TJ1040
THS1040IDW
Tube, 20
THS1040I
-40
C to 85
C
TJ1040
THS1040IDWR
Tube and Reel, 1000
For the most current specification and package information, refer to the TI web site at www.ti.com.
functional block diagram
SHA
10-Bit
ADC
ADC
Reference
Resistor
Digital
Control
3-State
Output
Buffers
Mode
Detection
BIASREF
AIN+
AIN-
MODE
REFSENSE
VREF
REFB
REFT
STBY
D (0-9)
OVR
OE
Timing
Circuit
CLK
AVDD
AGND
A2
VREF
DVDD
DGND
0.5 V
+
-
A1
NOTE: A1 - Internal bandgap reference
A2 - Internal ADC reference generator
THS1040
SLAS290C - OCTOBER 2001 - REVISED OCTOBER 2004
3
www.ti.com
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
1, 19
I
Analog ground
AIN+
27
I
Positive analog input
AIN-
25
I
Negative analog input
AVDD
28
I
Analog supply
BIASREF
21
O
When the MODE pin is at AVDD, a buffered AVDD/2 is present at this pin that can be used by external input
biasing circuits. The output is high impedance when MODE is AGND or AVDD/2.
CLK
15
I
Clock input
DGND
14
I
Digital ground
DVDD
2
I
Digital supply
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
3
4
5
6
7
8
9
10
11
12
O
Digital data bit 0 (LSB)
Digital data bit 1
Digital data bit 2
Digital data bit 3
Digital data bit 4
Digital data bit 5
Digital data bit 6
Digital data bit 7
Digital data bit 8
Digital data bit 9 (MSB)
MODE
23
I
Operating mode select (AGND, AVDD/2, or AVDD)
OE
16
I
High to 3-state the data bus, low to enable the data bus
OVR
13
O
Out-of-range indicator
REFB
24
I/O
Bottom ADC reference voltage
REFSENSE
18
I
VREF mode control
REFT
22
I/O
Top ADC reference voltage
STBY
17
I
Drive high to power-down the THS1040
TEST
20
I
Production test pin. Tie to DVDD or DGND
VREF
26
I/O
Internal or external reference
THS1040
SLAS290C - OCTOBER 2001 - REVISED OCTOBER 2004
4
www.ti.com
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: AV
DD
to AGND, DV
DD
to DGND
-0.3 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND to DGND
-0.3 V to 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AV
DD
to DV
DD
-4 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE input voltage range, MODE to AGND
-0.3 V to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference voltage input range, REFT, REFB, to AGND
-0.3 V to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range, AIN to AGND
-0.3 V to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range, VREF to AGND
-0.3 V to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference output voltage range, VREF to AGND
-0.3 V to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock input voltage range, CLK to AGND
-0.3 V to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, digital input to DGND
-0.3 V to DV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital output voltage range, digital output to DGND
-0.3 V to DV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating junction temperature range, T
J
0
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds
300
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
over operating free-air temperature range TA, (unless otherwise noted)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Power Supply
Supply voltage
AVDD, DVDD
3
3
3.6
V
Analog and Reference Inputs
VREF input voltage
VI(VREF)
REFSENSE = AVDD
0.5
1
V
REFT input voltage
VI(REFT)
MODE = AGND
1.75
2
V
REFB input voltage
VI(REFB)
MODE = AGND
1
1.25
V
Reference input voltage
VI(REFT) - VI(REFB) MODE = AGND
0.5
1
V
Reference common mode voltage
(VI(REFT)
+ VI(REFB))/2
MODE = AGND
(AVDD/2) - 0.05
(AVDD/2) + 0.05
V
Analog input voltage differential (see Note 1)
VI(AIN)
REFSENSE = AGND
-1
1
V
Analog input voltage differential (see Note 1)
VI(AIN)
REFSENSE = VREF
-0.5
0.5
V
Analog input capacitance, CI
10
pF
Clock input (see Note 2)
0
AVDD
V
Digital Outputs
Maximum digital output load resistance
RL
100
k
Maximum digital output load capacitance
CL
10
pF
Digital Inputs
High-level input voltage, VIH
2.4
DVDD
V
Low-level input voltage, VIL
DGND
0.8
V
Clock frequency (see Note 3)
tc
f(CLK) = 5 MHz to 40 MHz 25
200
nS
Clock pulse duration
tw(CKL), tw(CKH)
f(CLK) = 40 MHz
11.25
12.5
13.75
nS
Operating free-air temperature, TA
THS1040C
0
70
C
Operating free-air temperature, TA
THS1040I
-40
85
C
NOTE 1: VI(AIN) is AIN+ - AIN- range, based on VI(REFT) - VI(REFB) = 1 V. Varies proportional to the VI(REFT) - VI(REFB) value. Input common mode
voltage is recommended to be AVDD/2.
NOTE 2: The clock pin is referenced to AVSS and powered by AVDD.
NOTE 3: Clock frequency can be extended to this range without degradation of performance.
THS1040
SLAS290C - OCTOBER 2001 - REVISED OCTOBER 2004
5
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electrical characteristics
over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference),
differential input range = 1 VPP and 2 VPP, TA = Tmin to Tmax (unless otherwise noted)
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVDD
Supply voltage
3
3.6
V
DVDD
Supply voltage
3
3.6
V
ICC
Operating supply current
See Note 4
33
40
mA
PD
Power dissipation
See Note 4
100
120
mW
PD(STBY)
Standby power
75
W
Power up time for all references from standby, t(PU)
10
F bypass
770
s
t(WU)
Wake-up time
See Note 5
45
s
REFT, REFB internal ADC reference voltages outputs (MODE = AV
DD
or AV
DD
/2) (See Note 6)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference voltage top, REFT
VREF = 0.5 V
AVDD = 3 V
1.75
V
Reference voltage top, REFT
VREF = 1 V
AVDD = 3 V
2
V
Reference voltage bottom, REFB
VREF = 0.5 V
AVDD = 3 V
1.25
V
Reference voltage bottom, REFB
VREF = 1 V
AVDD = 3 V
1
V
Input resistance between REFT and REFB
1.4
1.9
2.5
k
VREF (on-chip voltage reference generator)
PARAMETER
MIN
TYP
MAX
UNIT
Internal 0.5-V reference voltage (REFSENSE = VREF)
0.45
0.5
0.55
V
Internal 1-V reference voltage (REFSENSE = AGND)
0.95
1
1.05
V
Reference input resistance (REFSENSE = AVDD, MODE = AVDD/2 or AVDD)
7
14
21
k
dc accuracy
PARAMETER
MIN
TYP
MAX
UNIT
Resolution
10
Bits
INL
Integral nonlinearity (see definitions)
-1.5
0.75
1.5
LSB
DNL
Differential nonlinearity (see definitions)
-0.9
0.45
0.9
LSB
Zero error (see definitions)
-1.5
0.7
1.5
%FSR
Full-scale error (see definitions)
-3
2.2
3
%FSR
Missing code
No missing code assured
NOTE 4: Apply a -1 dBFS 10-KHz triangle wave at AIN+ and AIN- with an internal bandgap reference and ADC reference enabled, and BIASREF
enabled at AVDD/2. Any additional load at BIASREF or VREF may require additional current.
NOTE 5: Wake-up time is from the power-down state to accurate ADC samples being taken and is specified for MODE = AGND with external
reference sources applied to the device at the time of release of power-down, and an applied 40-MHz clock. Circuits that need to power
up are the bandgap, bias generator, ADC, and SHA.
NOTE 6: External reference values are listed in the Recommended Operating Conditions Table.