THS1230
3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH POWER DOWN
SLAS291A OCTOBER 2000 REVISED NOVEMBER 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
features
D
12-Bit Resolution, 30 MSPS
Analog-to-Digital Converter
D
Configurable Input Functions:
Single-Ended
Single-Ended With Offset
Differential
D
3.3-V Supply Operation
D
Internal Voltage Reference
D
Out-of-Range Indicator
D
Power-Down Mode
D
IF Undersampling
applications
D
Set Top Box (STB)
D
Camcorders
D
Digital Cameras
D
Copiers
D
Communications
D
Test Instruments
D
IF and Baseband Digitization
description
The THS1230 is a CMOS, low power, 12-bit, 30 MSPS analog-to-digital converter (ADC) that operates with a
3.3-V supply. The THS1230 gives circuit developers complete flexibility. The analog input to the THS1230 can
be either single-ended, single-ended with offset, or differential. The THS1230 provides a wide selection of
voltage references to match the user's design requirements. For more design flexibility, the internal reference
can be bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the
application. The out-of-range output is used to monitor any out-of-range condition in the THS1230's input range.
The speed, resolution, and single-supply operation of the THS1230 are suited for applications in set top box
(STB), video, multimedia, high-speed acquisition, and communications. The speed and resolution ideally suit
charge-couple device (CCD) input systems such as digital copiers, digital cameras, and camcorders. The wide
input voltage range between V
REFB
and V
REFT
allows the THS1230 to be designed into multiple systems.
The THS1230C is characterized for operation from 0
C to 70
C. The THS1230I is characterized for operation
from 40
C to 85
C.
AVAILABLE OPTIONS
TA
PACKAGED DEVICES
TA
28-TSSOP (PW)
28-SOIC (DW)
0
C to 70
C
THS1230CPW
THS1230CDW
40
C to 85
C
THS1230IPW
THS1230IDW
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
CON1
CON0
EXTREF
AIN+
AIN
AGND
AV
DD
REFT
REFB
OVRNG
D11
D10
D9
CLK
AV
DD
OE
D0
D1
D2
D3
D4
DV
DD
DGND
D5
D6
D7
D8
DW OR PW PACKAGE
(TOP VIEW)
THS1230
3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH POWER DOWN
SLAS291A OCTOBER 2000 REVISED NOVEMBER 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
12-Bit ADC
D[11:0]
Sample
and Hold
CLK
DGND
AGND
OVRNG
CON0
Timing Circuitry
REFT REFB
Internal
Reference
Circuit
CON1
3-State
Output
Buffers
EXTREF
Configuration
Control
Circuit
DVDD
AIN+
AIN
AVDD
OE
THS1230
3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH POWER DOWN
SLAS291A OCTOBER 2000 REVISED NOVEMBER 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
1, 7
I
Analog ground
AVDD
8, 27
I
Analog supply
AIN+
5
I
Positive analog input
AIN
6
I
Negative analog input
CLK
28
I
ADC conversion clock
CON1
2
I
Configuration Input 1
CON0
3
I
Configuration Input 0
DGND
19
I
Digital ground
DVDD
20
I
Digital supply
D11
12
O
ADC data bit 11
D10
13
O
ADC data bit 10
D9
14
O
ADC data bit 9
D8
15
O
ADC data bit 8
D7
16
O
ADC data bit 7
D6
17
O
ADC data bit 6
D5
18
O
ADC data bit 5
D4
21
O
ADC data bit 4
D3
22
O
ADC data bit 3
D2
23
O
ADC data bit 2
D1
24
O
ADC data bit 1
D0
25
O
ADC data bit 0
EXTREF
4
I
Reference select input, high = external, low = internal
OVRNG
11
O
Out of range indicator
OE
26
I
Output enable, high = disable, low = enable
REFT
9
I/O
Upper ADC reference voltage
REFB
10
I/O
Lower ADC reference voltage
THS1230
3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH POWER DOWN
SLAS291A OCTOBER 2000 REVISED NOVEMBER 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range:
AV
DD
to AGND, DV
DD
to DGND
0.3 to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND to DGND
0.3 to 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference voltage input range, REFT, REFB to AGND
0.3 to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range, AIN+, AIN to AGND
0.3 to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock input voltage range, CLK to AGND
0.3 to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, digital input to DGND
0.3 to DV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital output voltage range, digital output to DGND
0.3 to DV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating junction temperature range, T
J
40
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
STG
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds
300
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
electrical characteristics over recommended operating conditions (AV
DD
= DV
DD
= 3.3 V,
f
s
= 30 MHz/50% duty cycle, MODE = 1, 1-V input span, internal reference, T
min
to T
max
) ( unless
otherwise noted)
sampling rate and resolution
PARAMETER
MIN
NOM
MAX
UNIT
fs
Sample frequency
5
30
MSPS
Resolution
12
Bits
analog inputs (all supplies = 3.3 V)
PARAMETER
MIN
TYP
MAX
UNIT
Positive analog input, AIN+
0
AVDD
V
Negative analog input, AIN
0
AVDD
V
MODE1
1
V
Analog input voltage difference for zero scale ADC out, (AIN+) (AIN)
MODE2
2
V
MODE3
0
V
MODE1
1
V
Analog input voltage difference for full scale ADC out, (AIN+) (AIN)
MODE2
2
V
MODE3
1
V
Switched input capacitance, Ci
6
pF
Aperture delay time, td(ap)
2
ns
Aperture uncertainty (jitter)
2
ps
DC leakage current (input =
FS)
10
A
The clock frequency may be extended to 5 MHz without degradation in specified performance.
THS1230
3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH POWER DOWN
SLAS291A OCTOBER 2000 REVISED NOVEMBER 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (AV
DD
= DV
DD
= 3.3 V,
f
s
= 30 MHz/50% duty cycle, MODE = 1, 1-V input span, internal reference, T
min
to T
max
) (unless
otherwise noted) (continued)
digital inputs and outputs (all supplies = 3.3 V)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Digital Inputs
VIH
High level input voltage
All other inputs
0.8
DVDD
V
VIH
High level input voltage
CLK
0.8
AVDD
VIL
Low level input voltage
All other inputs
0.2
DVDD
V
VIL
Low level input voltage
CLK
0.2
AVDD
IIH
High level input current
1
A
IIL
Low level input current
1
A
Ci
Input capacitance
5
pF
Digital Outputs
VOH
High level output voltage
Iload = 50
A
DVDD0.4
V
VOL
Low level output voltage
Iload = 50
A
0.4
V
High impedance output current
1
A
tr/tf
Rise/fall time
CL = 10 pF
5.5
ns
power supply (CLK = 30 MHz)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
XVDD
Supply voltage (all supplies)
3
3.3
3.6
V
IDD
Supply current active total
48
66
mA
I(analog)
Supply current active analog
35
mA
I(digital)
Supply current active digital
13
mA
II(standby)
Standby supply current
CLK = 0 MHz
10
A
t(PU)
Power-up time for references from standby
100
s
PD
Power dissipation
CLK = 30 MHz
168
220
mW
PD(STBY)
Standby power dissipation
CLK = 0 MHz
36
W
PSRR
Power supply rejection ratio
0.1
%FS
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