THS5661

12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Member of the Pin-Compatible
CommsDAC

Product Family

100 MSPS Update Rate

12-Bit Resolution

Spurious Free Dynamic Range (SFDR) to
Nyquist at 20 MHz Output: 63 dBc

1 ns Setup/Hold Time

Differential Scalable Current Outputs: 2 mA
to 20 mA

On-Chip 1.2 V Reference

3 V and 5 V CMOS-Compatible Digital
Interface

Straight Binary or Twos Complement Input

Power Dissipation: 175 mW at 5 V, Sleep
Mode: 25 mW at 5 V

Package: 28-Pin SOIC and TSSOP

description

The THS5661 is a 12-bit resolution digital-to-analog converter (DAC) specifically optimized for digital data
transmission in wired and wireless communication systems. The 12-bit DAC is a member of the CommsDAC
series of high-speed, low-power CMOS digital-to-analog converters. The CommsDAC family consists of pin
compatible 14-, 12-, 10-, and 8-bit DACs. All devices offer identical interface options, small outline package, and
pinout. The THS5661 offers superior ac and dc performance while supporting update rates up to 100 MSPS.

The THS5661 operates from an analog supply of 4.5 V to 5.5 V. Its inherent low power dissipation of 175 mW
ensures that the device is well-suited for portable and low-power applications. Lowering the full-scale current
output reduces the power dissipation without significantly degrading performance. The device features a
SLEEP mode, which reduces the standby power to approximately 25 mW, thereby optimizing the power
consumption for system needs.

The THS5661 is manufactured in Texas Instruments advanced high-speed mixed-signal CMOS process. A
current-source-array architecture combined with simultaneous switching shows excellent dynamic
performance. On-chip edge-triggered input latches and a 1.2 V temperature-compensated bandgap reference
provide a complete monolithic DAC solution. The digital supply range of 3 V to 5.5 V supports 3 V and 5 V CMOS
logic families. Minimum data input setup and hold times allow for easy interfacing with external logic. The
THS5661 supports both a straight binary and twos complement input word format, enabling flexible interfacing
with digital signal processors.

The THS5661 provides a nominal full-scale differential output current of 20 mA and >300 k

output impedance,

supporting both single-ended and differential applications. The output current can be directly fed to the load
(e.g., external resistor load or transformer), with no additional external output buffer required. An accurate
on-chip reference and control amplifier allows the user to adjust this output current from 20 mA down to 2 mA,
with no significant degradation of performance. This reduces power consumption and provides 20 dB gain range
control capabilities. Alternatively, an external reference voltage and control amplifier may be applied in
applications using a multiplying DAC. The output voltage compliance range is 1.25 V.

1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D11

D10

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

NC
NC

CLK
DV

DGND
MODE
AV

COMP2
IOUT1
IOUT2
AGND
COMP1
BIASJ
EXTIO
EXTLO
SLEEP

SOIC (DW) OR TSSOP (PW) PACKAGE

(TOP VIEW)

NC No internal connection

CommsDAC is a trademark of Texas Instruments Incorporated.

THS5661
12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description (continued)

The THS5661 is available in both a 28-pin SOIC and TSSOP package. The device is characterized for operation
over the industrial temperature range of 40

C to 85

AVAILABLE OPTIONS

PACKAGE

28-TSSOP

(PW)

28-SOIC

(DW)

C to 85

THS5661IPW

THS5661IDW

functional block diagram

IOUT1

IOUT2

CLK

D[11:0]

EXTLO

DGND

AVDD

EXTIO

COMP2

Current

Source

Array

Output

Current

Switches

AGND

1.2 V

REF

BIASJ

Control

AMP

0.1

2 k

I BIAS

COMP1

Logic

Control

1 nF

DVDD

RBIAS

SLEEP

MODE

RLOAD

CEXT

0.1

THS5661

12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AGND

Analog ground return for the internal analog circuitry

AVDD

Positive analog supply voltage (4.5 V to 5.5 V)

BIASJ

Full-scale output current bias

CLK

External clock input. Input data latched on rising edge of the clock.

COMP1

Compensation and decoupling node, requires a 0.1

F capacitor to AVDD.

COMP2

Internal bias node, requires a 0.1

F decoupling capacitor to AGND.

D[11:0]

[1:12]

Data bits 0 through 11.
D11 is most significant data bit (MSB), D0 is least significant data bit (LSB).

DGND

Digital ground return for the internal digital logic circuitry

DVDD

Positive digital supply voltage (3 V to 5.5 V)

EXTIO

I/O

Used as external reference input when internal reference is disabled (i.e., EXTLO = AVDD). Used as internal
reference output when EXTLO = AGND, requires a 0.1

F decoupling capacitor to AGND when used as reference

output.

EXTLO

Internal reference ground. Connect to AVDD to disable the internal reference source.

IOUT1

DAC current output. Full scale when all input bits are set 1

IOUT2

Complementary DAC current output. Full scale when all input bits are 0

MODE

Mode select. Internal pulldown. Mode 0 is selected if this pin is left floating or connected to DGND. See
timing diagram.

[13:14]

No connection

SLEEP

Asynchronous hardware power down input. Active high. Internal pulldown. Requires 5

s to power down but 3 ms

to power up.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, AV

(see Note 1)

0.3 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2)

0.3 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage between AGND and DGND

0.3 V to 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage range, AV

to DV

6.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLK, SLEEP, MODE (see Note 2)

0.3 V to DV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . .

Digital input D11D0 (see Note 2)

0.3 V to DV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . .

IOUT1, IOUT2 (see Note 1)

1 V to AV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

COMP1, COMP2 (see Note 1)

0.3 V to AV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . .

EXTIO, BIASJ (see Note 1)

0.3 V to AV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

EXTLO (see Note 1)

0.3 V to 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak input current (any input)

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak total input current (all inputs)

30 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

: THS5661I

C to 85

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds

260

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. Measured with respect to AGND.
2. Measured with respect to DGND.

THS5661
12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, AV

= 5 V,

= 5 V, IOUT

= 20 mA (unless otherwise noted)

dc specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

Bits

DC accuracy

INL

Integral nonlinearity

TA = 40

C to 85

0.75

LSB

DNL

Differential nonlinearity

TA = 40

C to 85

0.5

LSB

Monotonicity

At 11-bit level

Monotonic

Analog output

Offset error

0.02

%FSR

Gain error

Without internal reference

2.3

%FSR

Gain error

With internal reference

1.3

%FSR

Full scale output current

Output compliance range

AVDD = 5 V, IOUTFS = 20 mA

1.25

Output resistance

300

Output capacitance

Reference output

Reference voltage

1.18

1.22

1.32

Reference output current§

100

Reference input

VEXTIO

Input voltage range

0.1

1.25

Input resistance

Small signal bandwidth¶

Without CCOMP1

1.3

MHz

Input capacitance

100

Temperature coefficients

Offset drift

Gain drift

Without internal reference

ppm of

Gain drift

With internal reference

120

m of

FSR/

Reference voltage drift

Power supply

AVDD

Analog supply voltage

4.5

5.5

DVDD

Digital supply voltage

5.5

IAVDD

Analog supply current

IAVDD

Sleep mode supply current

Sleep mode

IDVDD

Digital supply current#

Power dissipation

AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA

175

AVDD

Power supply rejection ratio

0.4

%FSR/V

DVDD

Power supply rejection ratio

0.025

%FSR/V

Operating range

Measured at IOUT1 in virtual ground configuration.
Nominal full-scale current IOUTFS equals 32X the IBIAS current.

§ Use an external buffer amplifier with high impedance input to drive any external load.
¶ Reference bandwidth is a function of external cap at COMP1 pin and signal level.
# Measured at fCLK = 50 MSPS and fOUT= 1 MHz.

|| Measured for 50

RLOAD at IOUT1 and IOUT2, fCLK = 50 MSPS and fOUT = 20 MHz.

Specifications subject to change

THS5661

12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, AV

= 5 V,

= 5 V, IOUT

= 20 mA, differential transformer coupled output, 50

doubly terminated load

(unless otherwise noted)

ac specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog output

fCLK

Maximum output update rate

DVDD = 4.5 V to 5.5 V

100

MSPS

fCLK

Maximum output update rate

DVDD = 3 V to 3.6 V

MSPS

ts(DAC)

Output settling time to 0.1%

tpd

Output propagation delay

Glitch energy

Worst case LSB transition (code 2047 code 2048)

pV-s

tr(IOUT) Output rise time 10% to 90%

tf(IOUT)

Output fall time 90% to 10%

Output noise

IOUTFS = 20 mA

pA/

Output noise

IOUTFS = 2 mA

pA/

AC linearity

fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25

THD

Total harmonic distortion

fCLK = 50 MSPS, fOUT = 1 MHz, TA = 40

C to 85

dBc

THD

Total harmonic distortion

fCLK = 50 MSPS, fOUT = 2 MHz, TA = 25

dBc

fCLK = 100 MSPS, fOUT = 2 MHz, TA = 25

fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25

fCLK = 50 MSPS, fOUT= 1 MHz, TA = 40

C to 85

fCLK = 50 MSPS, fOUT = 1 MHz, TA = 25

dBc

Spurious free dynamic range to

fCLK = 50 MSPS, fOUT = 2.51 MHz, TA = 25

dBc

Spurious free dynamic range to

Nyquist

fCLK = 50 MSPS, fOUT = 5.02 MHz, TA = 25

SFDR

Nyquist

fCLK = 50 MSPS, fOUT = 20.2 MHz, TA = 25

SFDR

fCLK = 100 MSPS, fOUT = 5.04 MHz, TA = 25

dBc

fCLK = 100 MSPS, fOUT = 20.2 MHz, TA = 25

dBc

fCLK = 100 MSPS, fOUT = 40.4 MHz, TA = 25

dBc

Spurious free dynamic range

fCLK = 50 MSPS, fOUT = 1 MHz, TA= 25

C,1 MHz span

Spurious free dynamic range

within a window

fCLK = 50 MSPS, fOUT = 5.02 MHz, 2 MHz span

dBc

within a window

fCLK = 100 MSPS, fOUT= 5.04 MHz, 4 MHz span

Measured single ended into 50

load at IOUT1.

Single-ended output IOUT1, 50

doubly terminated load.

THS5661
12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, AV

= 5 V,

= 5 V, IOUT

= 20 mA (unless otherwise noted)

digital specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Interface

VIH

High level input voltage

DVDD = 5 V

3.5

VIH

High-level input voltage

DVDD = 3.3 V

2.1

3.3

VIL

Low level input voltage

DVDD = 5 V

1.3

VIL

Low-level input voltage

DVDD = 3.3 V

0.9

IIH

High-level input current

DVDD = 3 V to 5.5 V

IIL

Low-level input current

DVDD = 3 V to 5.5 V

Input capacitance

Timing

tsu(D)

Input setup time

th(D)

Input hold time

tw(LPH)

Input latch pulse high time

td(D)

Digital delay time

clk

Specifications subject to change

THS5661

12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

fCLK = 100 MSPS

Figure 1

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 0 dBFS

Fout MHz

fCLK = 5 MSPS

SFDR dBc

fCLK = 25 MSPS

fCLK = 50 MSPS

fCLK = 70 MSPS

Figure 2

0.5

1.0

1.5

2.0

2.5

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 5 MSPS

Fout MHz

0 dBFS

SFDR dBc

6 dBFS

12 dBFS

Figure 3

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 25 MSPS

Fout MHz

6 dBFS

SFDR dBc

12 dBFS

0 dBFS

Figure 4

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 50 MSPS

Fout MHz

6 dBFS

SFDR dBc

12 dBFS

0 dBFS

DD = DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50

doubly terminated load, TA = 25

C (unless otherwise

noted.)

THS5661
12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 5

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 70 MSPS

Fout MHz

SFDR dBc

12 dBFS

6 dBFS

0 dBFS

Figure 6

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 100 MSPS

Fout MHz

SFDR dBc

12 dBFS

6 dBFS

0 dBFS

27

24

21

18

15

12

Figure 7

4.55 MHz @ 50 MSPS

SPURIOUS FREE DYNAMIC RANGE

AOUT AT FOUT = FCLOCK/11

Aout dBFS

SFDR dBc

2.27 MHz @ 25 MSPS

6.36 MHz @ 70 MSPS

9.1 MHz @ 100 MSPS

27

24

21

18

15

12

Figure 8

5 MHz @ 25 MSPS

SPURIOUS FREE DYNAMIC RANGE

AOUT AT FOUT = FCLOCK/5

Aout dBFS

SFDR dBc

10 MHz @ 50 MSPS

20 MHz @ 100 MSPS

14 MHz @ 70 MSPS

DD = DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50

doubly terminated load, TA = 25

C (unless otherwise

noted.)

THS5661

12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 9

30 27 24 21 18 15 12

DUAL TONE SPURIOUS FREE DYNAMIC RANGE

AOUT AT FOUT = FCLOCK/7

Aout dBFS

SFDR dBc

0.675/0.725 MHz @ 5 MSPS

13.5/14.5 MHz @ 100 MSPS

9.67/10.43 MHz @ 70 MSPS

3.38/3.63 MHz @ 25 MSPS

6.75/7.25 MHz @ 50 MSPS

90

84

78

72

66

100

120

Figure 10

TOTAL HARMONIC DISTORTION

CLOCK FREQUENCY AT FOUT = 2 MHZ

Fclock MSPS

THD dBc

2nd Harmonic

3rd Harmonic

4th Harmonic

Figure 11

SPURIOUS FREE DYNAMIC RANGE

FULL-SCALE OUTPUT CURRENT

IoutFS mA

Fout = 2.5 MHz

SFDR dBc

Fout = 10 MHz

Fout = 40 MHz

Fout = 28.6 MHz

Figure 12

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 100 MSPS

Fout MHz

SFDR dBc

Differential @ 6 dBFS

Differential @ 0 dBFS

Single-ended @ 0 dBFS

Single-ended @ 6 dBFS

DD = DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50

doubly terminated load, TA = 25

C (unless otherwise

noted.)

THS5661

12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 15

0.5

0.25

0.00

0.25

0.50

512

1024

1536

2048

2560

3072

3584

4096

DNL

 Differential Nonlinearity LSB

Code

DIFFERENTIAL NONLINEARITY

Figure 16

Amplitude dBm

SINGLE-TONE OUTPUT SPECTRUM

100

90

80

70

60

50

40

30

20

10

Fout = 5 MHz at
Fclock = 50 MSPS

Frequency MHz

Figure 17

Amplitude dBm

SINGLE-TONE OUTPUT SPECTRUM

100

90

80

70

60

50

40

30

20

10

Fout = 10 MHz at
Fclock = 100 MSPS

Frequency MHz

DD = DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50

doubly terminated load, TA = 25

C (unless otherwise

noted.)

THS5661

12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 20

SUPPLY CURRENT

OUTPUT FULL-SCALE OUTPUT CURRENT

IOUTFS Full-Scale Output Current mA

I(A

VDD) Supply Current mA

Figure 21

0.1

0.2

0.3

0.4

0.5

DIGITAL SUPPLY CURRENT

RATIO (Fclock/Fout) AT DV

= 5 V

Ratio (Fclock/Fout)

100 MSPS

I(DVDD) Supply Current mA

70 MSPS

50 MSPS

25 MSPS

5 MSPS

Figure 22

0.1

0.2

0.3

0.4

0.5

5 MSPS

DIGITAL SUPPLY CURRENT

RATIO (Fclock/Fout) AT DV

= 3.3 V

Ratio (Fclock/Fout)

I(DVDD) Supply Current mA

25 MSPS

50 MSPS

70 MSPS

DD = DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50

doubly terminated load, TA = 25

C (unless otherwise

noted.)

THS5661
12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

The THS5661 architecture is based on current steering, combining high update rates with low power
consumption. The CMOS device consists of a segmented array of PMOS transistor current sources, which are
capable of delivering a full-scale current up to 20 mA. High-speed differential current switches direct the current
of each current source to either one of the output nodes, IOUT1 or IOUT2. The complementary output currents
thus enable differential operation, canceling out common mode noise sources (on-chip and PCB noise), dc
offsets, even order distortion components, and increase signal output power by a factor of two. Major
advantages of the segmented architecture are minimum glitch energy, excellent DNL, and very good dynamic
performance. The DAC's high output impedance of >300 k

and fast switching result in excellent dynamic

linearity (spurious free dynamic range SFDR).

The full-scale output current is set using an external resistor R

BIAS

in combination with an on-chip bandgap

voltage reference source (1.2 V) and control amplifier. The current I

BIAS

through resistor R

BIAS

is mirrored

internally to provide a full-scale output current equal to 32 times I

BIAS

. The full-scale current can be adjusted

from 20 mA down to 2 mA.

data interface and timing

The THS5661 comprises separate analog and digital supplies, i.e. AV

and DV

. The digital supply voltage

can be set from 5.5 V down to 3 V, thus enabling flexible interfacing with external logic. The THS5661 provides
two operating modes, as shown in Table 1. Mode 0 (mode pin connected to DGND) supports a straight binary
input data word format, whereas mode 1 (mode pin connected to DV

) sets a twos complement input

configuration.

Figure 23 shows the timing diagram. Internal edge-triggered flip-flops latch the input word on the rising edge
of the input clock. The THS5661 provides for minimum setup and hold times (> 1 ns), allowing for noncritical
external interface timing. Conversion latency is one clock cycle for both modes. The clock duty cycle can be
chosen arbitrarily under the timing constraints listed in the digital specifications table. However, a 50% duty cycle
will give optimum dynamic performance. Figure 24 shows a schematic of the equivalent digital inputs of the
THS5661, valid for pins D11D0, SLEEP, and CLK. The digital inputs are CMOS-compatible with logic
thresholds of DV

20%. Since the THS5661 is capable of being updated up to 100 MSPS, the quality of

the clock and data input signals are important in achieving the optimum performance. The drivers of the digital
data interface circuitry should be specified to meet the minimum setup and hold times of the THS5661, as well
as its required min/max input logic level thresholds. Typically, the selection of the slowest logic family that
satisfies the above conditions will result in the lowest data feed-through and noise. Additionally, operating the
THS5661 with reduced logic swings and a corresponding digital supply (DV

) will reduce data feed-through.

Note that the update rate is limited to 67 MSPS for a digital supply voltage DV

of 3 V to 3.6 V.

THS5661
12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

DAC transfer function

The THS5661 delivers complementary output currents IOUT1 and IOUT2. Output current IOUT1 equals the
approximate full-scale output current when all input bits are set high in mode 0 (straight binary input), i.e. the
binary input word has the decimal representation 4095. For mode 1, the MSB is inverted (twos complement input
format). Full-scale output current will flow through terminal IOUT2 when all input bits are set low (mode 0,
straight binary input). The relation between IOUT1 and IOUT2 can thus be expressed as:

IOUT1

IOUT

IOUT2

where IOUT

is the full-scale output current. The output currents can be expressed as:

IOUT1

IOUT

CODE

4096

IOUT2

IOUT

(4095

CODE)

4096

where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drive
resistor loads R

LOAD

or a transformer with equivalent input load resistance R

LOAD

. This would translate into

single-ended voltages VOUT1 and VOUT2 at terminal IOUT1 and IOUT2, respectively, of:

VOUT1

IOUT1

LOAD

CODE

4096

IOUT

LOAD

VOUT2

IOUT2

LOAD

(4095CODE)

4096

IOUT

LOAD

The differential output voltage VOUT

DIFF

can thus be expressed as:

VOUT

DIFF

VOUT1VOUT2

(2CODE4095)

4096

IOUT

LOAD

The latter equation shows that applying the differential output will result in doubling of the signal power delivered
to the load. Since the output currents of IOUT1 and IOUT2 are complementary, they become additive when
processed differentially. Care should be taken not to exceed the compliance voltages at node IOUT1 and
IOUT2, which would lead to increased signal distortion.

THS5661

12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

reference operation

The THS5661 comprises a bandgap reference and control amplifier for biasing the full-scale output current. The
full-scale output current is set by applying an external resistor R

BIAS

. The bias current I

BIAS

through resistor

BIAS

is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current

equals 32 times this bias current. The full-scale output current IOUT

can thus be expressed as:

IOUT

BIAS

EXTIO

BIAS

where V

EXTIO

is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage

of 1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor
C

EXT

of 0.1

F should be connected externally to terminal EXTIO for compensation. The bandgap reference

can additionally be used for external reference operation. In that case, an external buffer with high impedance
input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference
can be disabled and overridden by an external reference by connecting EXTLO to AV

. Capacitor C

EXT

may

hence be omitted. Terminal EXTIO thus serves as either input or output node.

The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor R

BIAS

or changing

the externally applied reference voltage. The internal control amplifier has a wide input range, supporting the
full-scale output current range of 20 dB. The bandwidth of the internal control amplifier is defined by the internal
1 nF compensation capacitor at pin COMP1 and the external compensation capacitor C1. The relatively weak
internal control amplifier may be overridden by an externally applied amplifier with sufficient drive for the internal
1 nF load, as shown in Figure 25. This provides the user with more flexibility and higher bandwidths, which are
specifically attractive for gain control and multiplying DAC applications. Pin SLEEP should be connected to
AGND or left disconnected when an external control amplifier is used.

AVDD

1.2 V

REF

REF AMP

1 nF

AVDD

AGND

EXTLO

EXTIO

BIASJ

AVDD

IOUT1 or IOUT2

External

Control AMP

EXT Reference

Voltage

COMP1

SLEEP

Current Source Array

REXT

Internal

Control AMP

THS4041

Figure 25. Bypassing the Internal Reference and Control Amplifier

THS5661
12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

analog current outputs

Figure 26 shows a simplified schematic of the current source array output with corresponding switches.
Differential PMOS switches direct the current of each individual PMOS current source to either the positive
output node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined
by the stack of the current sources and differential switches, and is typically >300 k

in parallel with an output

capacitance of 5 pF.

Output nodes IOUT1 and IOUT2 have a negative compliance voltage of 1 V, determined by the CMOS process.
Beyond this value, transistor breakdown may occur, resulting in reduced reliability of the THS5661 device. The
positive output compliance depends on the full-scale output current IOUT

and positive supply voltage AV

The positive output compliance equals 1.25 V for AV

= 5 V and IOUT

= 20 mA. Exceeding the positive

compliance voltage adversely affects distortion performance and integral nonlinearity. The optimum distortion
performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUT1
and IOUT2 does not exceed 0.5 V (e.g. when applying a 50

doubly terminated load for 20 mA full-scale output

current). Applications requiring the THS5661 output (i.e., OUT1 and/or OUT2) to extend its output compliance
should size R

LOAD

accordingly.

AVDD

Current Source Array

IOUT1

IOUT2

RLOAD

Current
Sources

Switches

Figure 26. Equivalent Analog Current Output

Figure 27(a) shows the typical differential output configuration with two external matched resistor loads. The
nominal resistor load of 50

will give a differential output swing of 2 V

when applying a 20 mA full-scale output

current. The output impedance of the THS5661 depends slightly on the output voltage at nodes IOUT1 and
IOUT2. Consequently, for optimum dc integral nonlinearity, the configuration of Figure 27(b) should be chosen.
In this IV configuration, terminal IOUT1 is kept at virtual ground by the inverting operational amplifier. The
complementary output should be connected to ground to provide a dc current path for the current sources
switched to IOUT2. Note that the INL/DNL specifications for the THS5661 are measured with IOUT1 maintained
at virtual ground. The amplifier's maximum output swing and the DAC's full-scale output current determine the
value of the feedback resistor R

. Capacitor C

filters the steep edges of the THS5661 current output, thereby

reducing the operational amplifier slew-rate requirements. In this configuration, the op amp should operate on
a dual supply voltage due to its positive and negative output swing. Node IOUT1 should be selected if a
single-ended unipolar output is desirable.

THS5661

12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

IOUT2

IOUT1

IOUT2

IOUT1

VOUT

100

RFB

)

VOUT

)

(a)

(b)

CFB

THS4001
THS4011

Figure 27. Differential and Single-Ended Output Configuration

The THS5661 can be easily configured to drive a doubly terminated 50

cable. Figure 28(a) shows the

single-ended output configuration, where the output current IOUT1 flows into an equivalent load resistance of
25

. Node IOUT2 should be connected to ground or terminated with a resistor of 25

. Differential-to-single

conversion (e.g., for measurement purposes) can be performed using a properly selected RF transformer, as
shown in Figure 28(b). This configuration provides maximum rejection of common-mode noise sources and
even order distortion components, thereby doubling the power to the output. The center tap on the primary side
of the transformer is connected to AGND, enabling a dc current flow for both IOUT1 and IOUT2. Note that the
ac performance of the THS5661 is optimum and specified using this differential transformer coupled output,
limiting the voltage swing at IOUT1 and IOUT2 to

0.5 V.

IOUT2

IOUT1

VOUT

IOUT2

IOUT1

VOUT

100

(a)

(b)

1:1

Figure 28. Driving a Doubly Terminated 50

Cable

THS5661
12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

sleep mode

The THS5661 features a power-down mode that turns off the output current and reduces the supply current to
less than 5 mA over the analog supply range of 4.5 V to 5.5 V and temperature range. The power-down mode
is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD). An internal
pulldown circuit at node SLEEP ensures that the THS5661 is enabled if the input is left disconnected. Power-up
and power-down activation times depend on the value of external capacitor at node SLEEP. For a nominal
capacitor value of 0.1

F power down takes less than 5

s, and approximately 3 ms to power backup. The

SLEEP mode should not be used when an external control amplifier is used, as shown in Figure 25.

definitions of specifications and terminology

integral nonlinearity (INL)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.

differential nonlinearity (DNL)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.

offset error

Offset error is defined as the deviation of the output current from the ideal of zero at a digital input value of 0.

gain error

Gain error is the error in slope of the DAC transfer function.

signal-to-noise ratio + distortion (S/N+D or SINAD)

S/N+D or SINAD is the ratio of the rms value of the output signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in
decibels.

spurious free dynamic range (SFDR)

SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious
signal within a specified bandwidth. The value for SFDR is expressed in decibels.

total harmonic distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal
and is expressed in decibels.

output compliance range

The maximum and minimum allowable voltage of the output of the DAC, beyond which either saturation of the
output stage or breakdown may occur.

settling time

The time required for the output to settle within a specified error band.

glitch energy

The time integral of the analog value of the glitch transient.

THS5661

12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

definitions of specifications and terminology (continued)

offset drift

The change in offset error versus temperature from the ambient temperature (T

= 25

C) in ppm of full-scale

range per

gain drift

The change in gain error versus temperature from the ambient temperature (T

= 25

C) in ppm of full-scale

range per

reference voltage drift

The change in reference voltage error versus temperature from the ambient temperature (T

= 25

C) in ppm

of full-scale range per

THS5661 evaluation board

An evaluation module (EVM) board for the THS5661 digital-to-analog converter is available for evaluation. This
board allows the user the flexibility to operate the THS5661 in various configurations. Possible output
configurations include transformer coupled, resistor terminated, and inverting/noninverting amplifier outputs.
The digital inputs are designed to interface with the TMS320 C5000 or C6000 family of DSPs or to be driven
directly from various pattern generators with the onboard option to add a resistor network for proper load
termination.

See the

THS56x1 Evaluation Module User's Guide for more details (SLAU032).

THS5661
12-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

CLK

MODE

DVDD

DGND

AGND

EXTLO

EXTIO

BIASJ

COMP1

COMP2

IOUT1

IOUT2

SLEEP

NC3

NC4

THS5661

FB3

C12

0.1

C18

4.7

+5V

R24

49.9

R29

49.9

DAC[2..15]

DAC2 DAC3

DAC4

DAC5

DAC6

DAC7

DAC8

DAC9

DAC10

DAC1

DAC12

DAC13

DAC14

DAC15

DSP[2..15]

R4A

R10A

R10B

R10C

R10D

R10E

R10F

R10G

R4B

R10H

R5G

R5F

R5E

R5H

R4E

R4C

R4D

R4F

R4G

R4H

R5A R5B R5C R5D

T11TKK81

R25 TDB

~OE

R20

R18 49.9

DSP2

DSP3

DSP4

DVDCC

DSP5

+5V

DSP6

DSP7

DSP8

DSP9

DSP10

DSP1

DSP12

DSP13

DSP14

CLKOUT

DSP15

C17

0.1

R14

5 K

C13

0.1

C16

0.1

C32

C25

CLKOUT

DSP0

DSP1

~OE

0.1

DVDCC

10K

10 K

DVDCC

DSP0

DSP1

DSP2

DSP3

DSP4

DSP5

DSP6

DSP7

DSP8 DSP9 DSP10 DSP1

DSP12 DSP13 DSP14 DSP15

DAC0

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

DAC7

DAC8 DAC9 DAC10 DAC1

DAC12 DAC13 DAC14 DAC15

DIR

VCC

GND

SN74L

VT245B

DIR

VCC

GND

SN74L

VT245B

R23

100

R12

U6A

SN74AL

VC08

SN74HC1G32

0.1

0.01

C23

0.1

C24

C31

C30

0.1

C29

0.01

FB4

DVDCC

+5V

0.1

C10

0.1

DVDCC

Miscellanious

Digital

Bypass

Caps

R16

3.0 K

1.5 K

THS3001

R30

750

R28

750

R26

750

R27

750

R22

A B C

D E F

I/O

TROBE

PDAC

SN74AHC1G00

DVDCC

0.1

C15

C22

C21

0.1

0.01

FB2

+5V

AD1580BR

R15

2.94 K

R19

C19

4.7

C14

0.01

U6B

U6C

T1004D

TERNA

CONFIGURA

TION

C35

4.7

C34

0.1

C33

0.01

+5V

C28

4.7

C27

0.1

C26

0.01

U6D

R13

R17

R21

4.7

Figure 29.

Schematic

APPLICATION INFORMATION

D10

FB1

C20

THS5661

12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

Figure 34. Board Layout, Layer 5

Table 2. Bill of Materials

QTY

REF. DES

PART NUMBER

DESCRIPTION

MFG.

C1, C22, C31

1206ZC105KAT2A

Ceranucm 1

F, 10 V, X7R, 10%

AVX

C18, C19, C28, C35

ECSTOJY475

6.3 V, 4.7

F, tantalum

Panasonic

C15, C24, C4

ECSTOJY106

6.3 V, 10

F, tantalum

Panasonic

C25, C32

Ceramic, not installed, 50 V, X7R, 10%

C14, C2, C20, C26, C29, C33

12065C103KAT2A

Ceramic, 0.01

F, 50 V, X7R, 10%

AVX

C10, C11, C12, C13, C16,
C17, C21, C23, C27, C3, C30,
C34, C5, C6, C7, C8, C9

12065C104KAT2A

Ceramic, 0.1

F, 50 V, X7R, 10%

AVX

D1, D2

AND/AND5GA or equivalent

GREEN LED, 1206 size SM chip LED

FB1, FB2, FB3, FB4

27-43-037447

Fair-Rite SM beads #27-037447

FairRite

TSW-117-07-L-D or equivalent

34-Pin header for IDC

Samtec

KRMZ2 or equivalent

2 Terminal screw connector,
2TERM_CON

Lumberg

TSW-112-07-L-S or equivalent

Single row 12-pin header

Samtec

KRMZ3 or equivalent

3 Terminal screw connector

Lumberg

J5, J6, J7

142-0701-206 or equivalent

PCB Mount SMA jack, SMA_PCB_MT

Johnson Components

J8, J9

142-0701-206 or equivalent

PCB Mount SMA jack, not installed

Johnson Components

L1, L2, L3

DO1608C-472

DO1608C-series, DS1608C-472

Coil Craft

1206

1206 Chip resistor, 1.5K, 1/4 W, 1%

R10, R11, R4, R5

CTS/CTS766-163-(R)330-G-TR

8 Element isolated resistor pack, 33

THS5661
12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

Table 2. Bill of Materials (Continued)

QTY

REF. DES

PART NUMBER

DESCRIPTION

MFG.

R12, R19, R7, R9

1206

1206 Chip resistor, 33

, 1/4 W, 1%

R13, R17. R2, R21, R8

1206

1206 Chip resistor, 0

, 1/4 W, 1%

R14

3214W-1-502 E or equivalent

4 mm SM Pot, 5K

Bourns

R15

1206

1206 Chip resistor, 2.94K, 1/4 W, 1%

R16

1206

1206 Chip resistor, 3K, 1/4 W, 1%

R18, R24, R29

1206

1206 Chip resistor, 49.94K, 1/4 W, 1%

R20, R3, R6

1206

1206 Chip resistor, 10K, 1/4 W, 1%

R22

1206

1206 Chip resistor, 10K, 1/4 W, 1%

R23

1206

1206 Chip resistor, 100K, 1/4 W, 1%

R25

1206

1206 Chip resistor, TBD, 1/4 W, 1%

R26, R27, R28, R30

1206

1206 Chip resistor, 750K, 1/4 W, 1%

T1-1T-KK81

RF Transformer, T1-1T-KK81

MiniCircuits

U1, U2

SN74LVT245BDW

Octal bus transceiver, 3-state,
SN74LVT245B

SN74AHCT1G00DBVR/
SN74AHC1G00DBVR

Single gate NAND, SN74AHC1G00

SN74AHCT1G32DBVR/
SN74AHCC1G32DBVR

Single 2 input positive or gate,
SN74AHC1G32

THS5641

THS5641IDW

DAC, 2.75.5 V, 8 Bit, 125 MHz

THS5651

THS5651IDW

DAC, 2.75.5 V, 10 Bit, 125 MHz

THS5661

THS5661IDW

DAC, 2.75.5 V, 12 Bit, 125 MHz

THS5671

THS5647IDW

DAC, 2.75.5 V, 14 Bit, 125 MHz

SN74ALVC08

SN74ALVC08D

Quad AND gate

LT1004D

LT1004CD-1-2/LT1004ID-1-2

Precision 1.2 V reference

NOT INSTALLED

AD1580BRT

Precision voltage reference, not
installed

THS3001

THS3001CD/THS2001ID

THS3001 high-speed op amp

TSW-102-07-L-S or equivalent

2 position jumper_.1'' spacing, W2

Samtec

TSW-102-07-L-S or equivalent

3 position jumper_.1'' spacing, W3

Samtec

2X3_JUMPER

TSW-102-07-L-S or equivalent

6-Pin header dual row, 0.025

0.1,

2X3_JUMPER

Samtec

THS5661

12-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS200A MAY 1999 REVISED JULY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MECHANICAL DATA

DW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

16 PINS SHOWN

4040000 / C 07/96

Seating Plane

0.400 (10,15)

0.419 (10,65)

0.104 (2,65) MAX

0.012 (0,30)

0.004 (0,10)

0.020 (0,51)

0.014 (0,35)

0.293 (7,45)

0.299 (7,59)

0.010 (0,25)

0.050 (1,27)

0.016 (0,40)

(15,24)

(15,49)

PINS **

0.010 (0,25) NOM

A MAX

DIM

A MIN

Gage Plane

0.500

(12,70)

(12,95)

0.510

(10,16)

(10,41)

0.400

0.410

0.600

0.610

(17,78)

0.700

(18,03)

0.710

0.004 (0,10)

0.010 (0,25)

0.050 (1,27)

 8

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER'S RISK.

In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI's publication of information regarding any third
party's products or services does not constitute TI's approval, warranty or endorsement thereof.

1999, Texas Instruments Incorporated

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