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Электронный компонент: TIBPAL22V10ACFN

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TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT
TM
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 D2943, OCTOBER 1986 REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1992, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Second-Generation PLD Architecture
Choice of Operating Speeds
TIBPAL22V10AC . . . 25 ns Max
TIBPAL22V10AM . . . 30 ns Max
TIBPAL22V10C . . . 35 ns Max
Increased Logic Power Up to 22 Inputs
and 10 Outputs
Increased Product Terms Average of 12
Per Output
Variable Product Term Distribution
Allows More Complex Functions to Be
Implemented
Each Output Is User Programmable for
Registered or Combinational Operation,
Polarity, and Output Enable Control
TTL-Level Preload for Improved Testability
Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability
Fast Programming, High Programming
Yield, and Unsurpassed Reliability Ensured
Using Ti-W Fuses
AC and DC Testing Done at the Factory
Utilizing Special Designed-In Test Features
Dependable Texas Instruments Quality and
Reliability
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
Functionally Equivalent to AMDs
AMPAL22V10 and AMPAL22V10A
description
The TIBPAL22V10 and TIBPAL22V10A are programmable array logic devices featuring high speed and
functional equivalency when compared to presently available devices. They are implemented with the familiar
sum-of-products (AND-OR) logic structure featuring the new concept "Programmable Output Logic Macrocell".
These IMPACT
TM
circuits combine the latest Advanced Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic.
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and
programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered
and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are
enabled through the use of individual product terms.
These devices are covered by U.S. Patent 4,410,987.
IMPACT is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/I
I
I
I
I
I
I
I
I
I
I
GND
V
CC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
C SUFFIX . . . NT PACKAGE
M SUFFIX . . . JT PACKAGE
(TOP VIEW)
3 2 1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
I
I
I
NC
I
I
I
4
26
14 15 16 17 18
I
I
GND
NC
I
I/O/Q
I/O/Q
I
I
CLK/I
NC
I/O/Q
I/O/Q
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
NC
No internal connection
Pin assignments in operating mode
V
CC
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT
TM
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 D2943, OCTOBER 1986 REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2
description (continued)
Further advantages can be seen in the introduction of variable product term distribution. This technique
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This
variable allocation of terms allows far more complex functions to be implemented than in previously available
devices.
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These
functions are common to all registers. When the synchronous set product term is a logic 1, the output registers
are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term
is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on
the polarity selected during programming. Output registers can be preloaded to any desired state during testing.
Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product term distribution, the
TIBPAL22V10 and TIBPAL22V10A offer quick design and development of custom LSI functions with
complexities of 500 to 800 equivalent gates. Since each of the ten output pins may be individually configured
as inputs on either a temporary or permanent basis, functions requiring up to 21 inputs and a single output or
down to 12 inputs and 10 outputs are possible.
A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is
applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered
outputs selected as active-high power up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once
blown, the verification circuitry is disabled and all other fuses will appear to be open.
The TIBPAL22V10C and TIBPAL22V10AC are characterized for operation from 0
C to 75
C. The
TIBPAL22V10AM is characterized for operation over the full military temperature range of 55
C to125
C.
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT
TM
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 D2943, OCTOBER 1986 REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
functional block diagram (positive logic)
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
10
12
14
EN
16
16
14
12
10
22
22
1
10
&
44 x 132
I/O/Q
I/O/Q
I/O/Q
I/O/Q
EN
EN
EN
EN
EN
EN
EN
EN
EN
10
10
8
8
10
11
CLK/I
I
Set
Reset
1S
R
C1
denotes fused inputs
Output
Logic
Macrocell
TIBP
AL22V10C, TIBP
AL22V10AC, TIBP
AL22V10AM
HIGH-PERFORMANCE
IMP
ACT
TM

PROGRAMMABLE ARRA
Y LOGIC CIRCUITS
SRPS024

D2943,
OCT
OBER 1986 REVISED MARCH 1992
POST
OFFICE BOX 655303
DALLAS, TEXAS 75265
4
0
4
8
12
16
20
24
28
Increments
First
Fuse
Numbers
32
36
40
Macro-
cell
R = 5809
P = 5808
R = 5811
P = 5810
R = 5813
P = 5812
R = 5815
P = 5814
R = 5817
P = 5816
logic symbol (positive logic)
Asynchronous Reset
23
22
21
20
19
1
2
3
4
5
(to all registers)
396
0
440
880
924
1452
1496
2112
2156
2860
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I
I
I
CLK/I
Macro-
cell
Macro-
cell
Macro-
cell
Macro-
cell
TIBP
AL22V10C, TIBP
AL22V10AC, TIBP
AL22V10AM
HIGH-PERFORMANCE
IMP
ACT
TM

PROGRAMMABLE ARRA
Y LOGIC CIRCUITS
SRPS024

D2943,
OCT
OBER 1986 REVISED MARCH 1992
POST
OFFICE BOX 655303
DALLAS, TEXAS 75265
5
Fuse number = First fuse number + Increment
R = 5819
P = 5818
R = 5821
P = 5820
R = 5823
P = 5822
R = 5825
P = 5824
R = 5827
P = 5826
18
6
7
8
9
10
11
17
16
15
14
Synchronous Set
13
(to all registers)
Inside each MACROCELL the "P" fuse is the polarity fuse and the "R" fuse is the register fuse.
2904
3608
3652
4268
4312
4840
4884
5324
5368
5720
5764
I
I
I
I
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
Macro-
cell
Macro-
cell
Macro-
cell
Macro-
cell
Macro-
cell
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT
TM
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 D2943, OCTOBER 1986 REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
6
output logic macrocell diagram
C1
G
0
3
0
1
1
0
3
2
MUX
I = 0
1S
1D
R
MUX
G1
1
1
SS
AR
From Clock Buffer
S1
S0
AR = asynchronous reset
SS = synchronous set
Output Logic Macrocell
FEEDBACK AND OUTPUT CONFIGURATION
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT
TM
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 D2943, OCTOBER 1986 REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
7
C1
1S
1D
R
S1 = 0
S0 = 0
C1
1S
1D
R
S1 = 0
S0 = 1
REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT
REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT
S1 = 1
S0 = 0
S1 = 1
S0 = 1
I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT
I/O FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT
MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE
FUSE SELECT
S1
S0
0
0
Register feedback
Registered
Active low
0
1
Register feedback
Registered
Active high
1
0
I/O feedback
Combinational
Active low
1
1
I/O feedback
Combinational
Active high
0 = unblown fuse, 1 = blown fuse
S1 and S0 are select-function fuses as shown in the output logic macrocell
diagram.
Figure 1. Resultant Macrocell Feedback and Output Logic After Programming
ns
Pulse duration
tw
ns
tsu
Setup time before clock
UNIT
TIBPAL22V10C, TIBPAL22V10AC
HIGH-PERFORMANCE IMPACT
TM
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 D2943, OCTOBER 1986 REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
8
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
(see Note 1)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1)
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to disabled output (see Note 1)
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range
0
C to 75
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
TIBPAL22V10C
TIBPAL22V10AC
MIN
NOM
MAX
MIN
NOM
MAX
VCC
Supply voltage
4.75
5
5.25
4.75
5
5.25
V
VIH
High-level input voltage
2
5.5
2
5.5
V
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
3.2
3.2
mA
IOL
Low-level output current
16
16
mA
fclock
Clock frequency
18
28.5
MHz
Clock high or low
25
15
Asynchronous reset high or low
35
25
Input
30
20
Feedback
30
20
Synchronous set
30
25
Asynchronous reset low (inactive)
35
25
th
Hold time, input, set, or feedback after clock
0
0
ns
TA
Operating free-air temperature
0
75
0
75
C
fclock (with feedback) =
1
tsu
)
t
pd
(CLK to Q)
, fclock (without feedback) =
1
tw(low)
)
tw(high)
IIL
VCC = 5.25 V,
VI = 0.4 V
A
UNIT
TEST CONDITIONS
PARAMETER
TEST CONDITIONS
PARAMETER
UNIT
TIBPAL22V10C, TIBPAL22V10AC
HIGH-PERFORMANCE IMPACT
TM
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 D2943, OCTOBER 1986 REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
9
electrical characteristics over recommended operating free-air temperature range
TIBPAL22V10C
TIBPAL22V10AC
MIN
TYP
MAX
MIN
TYP
MAX
VIK
VCC = 4.75 V, II = 18 mA
1.2
1.2
V
VOH
VCC = 4.75 V, IOH = 3.2 mA
2.4
3.5
2.4
3.5
V
VOL
VCC = 4.75 V, IOL = 16 mA
0.35
0.5
0.35
0.5
V
IOZH
VCC = 5.25 V, VO = 2.7 V
0.1
0.1
mA
Any output
100
100
Any I/O
250
250
II
VCC = 5.25 V, VI = 5.5 V
1
1
mA
IIH
VCC = 5.25 V, VI = 2.7 V
25
25
A
IIL
VCC = 5.25 V, VI = 0.4 V
0.25
0.25
mA
IOS
VCC = 5.25 V, VO = 0.5 V
30
90
30
90
mA
ICC
VCC = 5.25 V, VI = GND,
Outputs open
120
180
120
180
mA
switching characteristics
over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
TO
TIBPAL22V10C
TIBPAL22V10AC
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
TYP
MAX
fmax
With feedback
18
28.5
MHz
tpd
I, I/O
I/O
R1 = 300
,
15
35
15
25
ns
tpd
I, I/O (reset)
Q
R2 = 390
,
15
40
15
30
ns
tpd
CLK
Q
See Figure 4
10
25
10
15
ns
ten
I, I/O
I/O, Q
15
35
15
25
ns
tdis
I, I/O
I/O, Q
15
35
15
25
ns
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
fmax (with feedback) =
1
tsu
)
t
pd
(CLK to Q)
, fmax (without feedback) =
1
tw(low)
)
tw(high)
ns
Pulse duration
tw
ns
tsu
Setup time before clock
TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT
TM
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 D2943, OCTOBER 1986 REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
10
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
(see Note 1)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1)
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to disabled output (see Note 1)
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range
55
C to 125
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2
5.5
V
VIL
Low-level input voltage
0.8
V
IOH
High-level output current
2
mA
IOL
Low-level output current
12
mA
fclock
Clock frequency
22
MHz
Clock high or low
20
Asynchronous reset high or low
30
Input
25
Feedback
25
Synchronous set
25
Asynchronous reset low (inactive)
30
th
Hold time, input, set, or feedback after clock
0
ns
TA
Operating free-air temperature
55
125
C
fclock (with feedback) =
1
tsu
)
t
pd
(CLK to Q)
, fclock (without feedback) =
1
tw(low)
)
tw(high)
TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT
TM
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 D2943, OCTOBER 1986 REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
11
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
V
VOH
VCC = 4.5 V,
IOH = 2 mA
2.4
3.5
V
VOL
VCC = 4.5 V,
IOL = 12 mA
0.25
0.5
V
IOZH
VCC = 5.5 V,
VO = 2.7 V
0.1
mA
IOZL
VCC = 5.5 V,
VO = 0.4 V
100
A
II
VCC = 5.5 V,
VI = 5.5 V
1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
25
A
IIL
VCC = 5.5 V,
VI = 0.4 V
0.25
mA
IOS
VCC = 5.5 V,
VO = 0.5 V
30
90
mA
ICC
VCC = 5.5 V,
VI = GND,
Outputs open
120
180
mA
switching characteristics
over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fmax
With feedback
22
MHz
tpd
I, I/O
I/O
R1 = 390
,
15
30
ns
tpd
I, I/O (reset)
Q
R2 = 750
,
15
35
ns
tpd
CLK
Q
See Figure 4
10
20
ns
ten
I, I/O
I/O, Q
15
30
ns
tdis
I, I/O
I/O, Q
15
30
ns
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
fmax (with feedback) =
1
tsu
)
t
pd
(CLK to Q)
, fmax (without feedback) =
1
tw(low)
)
tw(high)
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT
TM
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 D2943, OCTOBER 1986 REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
12
preload procedure for registered outputs (see Notes 2 and 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below:
Step 1. With V
CC
at 5 V and pin 1 at V
IL
, raise pin 13 to V
IHH
.
Step 2. Apply either V
IL
or V
IH
to the output corresponding to the register to be preloaded.
Step 3. Pulse pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower pin 13 to V
IL
. Preload can be verified by observing the voltage level
at the output pin.
td
tsu
tw
td
VIHH
VIL
VIL
VOL
VOH
VIH
Pin 13
Pin 1
Registered I/O
Input
Output
VIH
VIL
Figure 2. Preload Waveforms
NOTES: 2. Pin numbers shown are for JT and NT packages only. If chip-carrier socket adapter is not used, pin numbers must be changed
accordingly.
3.
t
d =
t
su =
t
w
= 100 ns to 1000 ns.
V
IHH
= 10.25 V to 10.75 V.
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT
TM
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 D2943, OCTOBER 1986 REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
13
power-up reset
Following power up, all registers are reset to zero. The output level depends on the polarity selected during
programming. This feature provides extra flexibility to the system designer and is especially valuable in
simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of V
CC
be
monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and
feedback setup times are met.
1.5 V
tsu
tpd
tw
VOL
VOH
VIL
VIH
5 V
VCC
Active High
Registered Output
Active Low
Registered Output
CLK
4 V
VOH
VOL
1.5 V
1.5 V
(600 ns typ, 1000 ns MAX)
State Unknown
1.5 V
State Unknown
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 3. Power-Up Reset Waveforms
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT
TM
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 D2943, OCTOBER 1986 REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
14
PARAMETER MEASUREMENT INFORMATION
tsu
S1
R2
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
(3.5 V) [3 V]
(0.3 V) [0]
1.5 V
1.5 V
th
1.5 V
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
1.5 V
1.5 V
1.5 V
1.5 V
tw
1.5 V
1.5 V
3.3 V
VOL
VOH
VOH 0.5 V
0 V
ten
ten
tdis
tdis
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
R1
VOL
+
0.5 V
5 V
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
From Output
Under Test
Test
Point
Input
Out-of-Phase
Output
(see Note D)
Timing
Input
Data
Input
In-Phase
Output
High-Level
Pulse
Low-Level
Pulse
Output
Control
(lowlevel
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ). PRR
1 MHz,
tr = tf
2 ns, duty cycle = 50%. For M suffix, use the voltage levels indicated in brackets [ ]. PRR
10 MHz, tr and tf
2 ns,
duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 4. Load Circuit and Voltage Waveforms
B0892
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