TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D AUGUST 1989 REVISED MARCH 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Capable of Running With All Existing
TL16C450 Software

After Reset, All Registers Are Identical to
the TL16C450 Register Set

In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU

In the TL16C450 Mode, Holding and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data

Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2

 1) and Generates an Internal 16

Clock

Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream

Independent Receiver Clock Input

Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled

Fully Programmable Serial Interface
Characteristics:
5-, 6-, 7-, or 8-Bit Characters
Even-, Odd-, or No-Parity Bit Generation

and Detection

1-, 1 1/2-, or 2-Stop Bit Generation
Baud Generation (dc to 256 Kbit/s)

False-Start Bit Detection

Complete Status Reporting Capabilities

3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus

Line Break Generation and Detection

Internal Diagnostic Capabilities:
Loopback Controls for Communications

Link Fault Isolation

 Break, Parity, Overrun, Framing Error

Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)

Faster Plug-In Replacement for National
Semiconductor NS16550A

description

The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE).
Functionally identical to the TL16C450 on power up (character mode

), the TL16C550A can be placed in an

alternate mode (FIFO) to relieve the CPU of excessive software overhead.

In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver
FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system
efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package
and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address
(DMA) transfers.

The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem
and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of
the ACE at any point in the ACE's operation. Reported status information includes the type of transfer operation
in progress, the status of the operation, and any error conditions encountered.

The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of
dividing a reference clock input by divisors from 1 to (2

1) and producing a 16

clock for driving the internal

transmitter logic. Provisions are included to use this 16

clock to drive the receiver logic. Also included in the

ACE is a complete modem control capability and a processor interrupt system that may be software tailored
to the user's requirements to minimize the computing required to handle the communications link.

The TL16C550A can also be reset to the TL16C450 mode under software control.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1996, Texas Instruments Incorporated

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D AUGUST 1989 REVISED MARCH 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

block diagram

Receiver

Buffer

Register

Divisor

Latch (LS)

Divisor

Latch (MS)

Baud

Generator

Receiver

FIFO

Line

Status

Register

Transmitter

Holding

Register

Modem
Control

Register

Modem

Status

Register

Receiver

Buffer

Register

Line

Control

Register

Receiver

Timing and

Control

Line

Control

Register

Transmitter

FIFO

e
c

Line

Control

Register

Modem
Control

Logic

Interrupt

Enable

Register

Interrupt

I/O

Register

FIFO

Control

Register

Select

and

Control

Logic

Power
Supply

Interrupt

Control

Logic

e
c

Line

Control

Register

BAUDOUT

SIN

RCLK

SOUT

RTS

CTS

DTR

DSR

DCD

OUT1

OUT2

INTRPT

CS0

CS1

CS2

ADS

RD1

RD2

WR1

WR2

DDIS

TXRDY

XIN

XOUT

RXRDY

D7 D0

8 1

Internal

Data Bus

VCC

VSS

NOTE A: Terminal numbers shown are for the N package.

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D AUGUST 1989 REVISED MARCH 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

A0
A1
A2

28 [31]
27 [30]
26 [29]

Register select. A0, A1, and A2 are used during read and write operations to select the ACE register to read from
or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS) signal description.

ADS

25 [28]

Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0,
CS1, CS2) drive the internal select logic directly; when high, the register select and chip select signals are held in
the state they were in when the low-to-high transition of ADS occurred.

BAUDOUT

15 [17]

Baud out. BAUDOUT is a 16

clock signal for the transmitter section of the ACE. The clock rate is established by

the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT
may also be used for the receiver section by tying this output to the RCLK input.

CS0
CS1
CS2

12 [14]
13 [15]
14 [16]

Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. If any of these inputs are
inactive, the ACE remains inactive. Refer to the ADS (address strobe) signal description.

CTS

36 [40]

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem
status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when CTS changes state, an
interrupt is generated.

D0 D7

1 8

[2 9]

I/O

Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information between the
ACE and the CPU.

DCD

38 [42]

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states
since the last read from the modem status register. If the modem status interrupt is enabled when the DCD changes
state, an interrupt is generated.

DDIS

23 [26]

Driver disable. This output is active (high) when the CPU is not reading data. When active, this output can disable
an external transceiver.

DSR

37 [41]

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem
status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when the DSR changes state,
an interrupt is generated.

DTR

33 [37]

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR is placed in the active state by setting the DTR bit of the modem control register to a high level.
DTR is placed in the inactive state either as a result of a master reset or during loop mode operation or clearing
bit 0 (DTR) of the modem control register.

INTRPT

30 [33]

Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four
conditions that cause an interrupt to be issued are: a receiver error, received data is available or timeout (FIFO mode
only), transmitter holding register empty, or an enabled modem status interrupt. The INTRPT output is reset
(deactivated) either when the interrupt is serviced or as a result of a master reset.

35 [39]

Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer
to Table 2.

OUT1
OUT2

34 [38]
31 [35]

Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting
their respective modem control register bits (OUT1 and OUT2) high. OUT1 and OUT2 are set to their inactive (high)
states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the
modem control register.

RCLK

9 [10]

Receiver clock. RCLK is the 16

baud rate clock for the receiver section of the ACE.

RD1
RD2

21 [24]
22 [25]

Read inputs. When either RD1 or RD2 are active (high or low respectively) while the ACE is selected, the CPU is
allowed to read status information or data from a selected ACE register. Only one of these inputs is required for
the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied low
or RD1 tied high).

Terminal numbers shown in brackets are for the FN package.

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D AUGUST 1989 REVISED MARCH 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

39 [43]

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status
register. Bit 2 (TERI) of the modem status register indicates that the RI input has transitioned from a low to a high
state since the last read from the modem status register. If the modem status interrupt is enabled when this transition
occurs, an interrupt is generated.

RTS

32 [36]

Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS
is set to its active state by setting the RTS modem control register bit, and is set to its inactive (high) state either
as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the modem control register.

RXRDY

29 [32]

Receiver ready output. Receiver direct memory access (DMA) signalling is available with RXRDY. When operating
in the FIFO mode, one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450
mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between
CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the
receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), if there is at least 1 character
in the receiver FIFO or receiver holding register, RXRDY is active (low). When RXRDY has been active but there
are no characters in the FIFO or holding register, RXRDY goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3
= 1), when the trigger level or the timeout has been reached, RXRDY goes active (low); when it has been active
but there are no more characters in the FIFO or holding register, it goes inactive (high).

SIN

10 [11]

Serial input. SIN is a serial data input from a connected communications device.

SOUT

11 [13]

Serial output. SOUT is a composite serial data output to a connected communication device. SOUT is set to the
marking (high) state as a result of master reset.

TXRDY

24 [27]

Transmitter ready output. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO mode,
one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450 mode, only DMA
mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles.
Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has
been filled.

VCC

40 [44]

5-V supply voltage

VSS

20 [22]

Supply common

WR1
WR2

18 [20]
19 [21]

Write inputs. When either WR1 or WR2 are active (high or low respectively) while the ACE is selected, the CPU
is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer
data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied low or WR1 tied high).

XIN
XOUT

16 [18]
17 [19]

I/O

External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

Terminal numbers shown in brackets are for the FN package.

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