TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B JANUARY 1994 REVISED AUGUST 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Capable of Running With All Existing
TL16C450 Software
D
After Reset, All Registers Are Identical to
the TL16C450 Register Set
D
In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU
D
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
D
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2
16
1) and Generates an Internal 16
Clock
D
Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
D
Independent Receiver Clock Input
D
Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
D
Fully Programmable Serial Interface
Characteristics:
5-, 6-, 7-, or 8-Bit Characters
Even-, Odd-, or No-Parity Bit Generation
and Detection
1-, 1 1/2-, or 2-Stop Bit Generation
Baud Generation (DC to 562 Kbit/s)
D
False-Start Bit Detection
D
Complete Status Reporting Capabilities
D
3-State Outputs Provide TTL Drive
Capabilities for Bidirectional Data Bus and
Control Bus
D
Line Break Generation and Detection
D
Internal Diagnostic Capabilities:
Loopback Controls for Communications
Link Fault Isolation
Break, Parity, Overrun, Framing Error
Simulation
D
Fully Prioritized Interrupt System Controls
D
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
D
Faster Plug-In Replacement for National
Semiconductor NS16550A
description
The TL16C550B and the TL16C550BI are functional upgrades of the TL16C450 asynchronous
communications element (ACE). Functionally identical to the TL16C450 on power up (character mode
), the
TL16C550B and TL16C550BI can be placed in an alternate mode (FIFO) to relieve the CPU of excessive
software overhead.
In this alternate FIFO mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte
in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and
maximize system efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (RXRDY and
TXRDY) have been changed to allow signalling of DMA transfers.
The TL16C550B and the TL16C550BI perform serial-to-parallel conversions on data received from a peripheral
device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report
on the status of the ACE at any point in the ACE operation. Reported status information includes: the type of
transfer operation in progress, the status of the operation, and any error conditions encountered.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
The TL16C550B and the TL16C550BI can also be reset to the TL16C450 mode under software control.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1996, Texas Instruments Incorporated
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B JANUARY 1994 REVISED AUGUST 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The TL16C550B and the TL16C550BI ACE include programmable, on-board, baud rate generators. These
generators are capable of dividing a reference clock input by divisors from 1 to (2
16
1) and producing a 16
clock for driving the internal transmitter logic. Provisions are included to use this 16
clock to drive the receiver
logic. Also included in the ACE is a complete modem control capability and a processor interrupt system that
may be software tailored to user requirements to minimize the computing required to handle the
communications link.
The TL16C550B is available in a 40-pin DIP (N) package, 44-pin PLCC (FN) package, and 48-pin TQFP (PT)
package. The TL16C550BI is available in a 44-pin PLCC (FN) package.
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B JANUARY 1994 REVISED AUGUST 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CS0
CS1
CS2
BAUDOUT
XIN
XOUT
WR1
WR2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
RI
DCD
DSR
CTS
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
ADS
TXRDY
DDIS
RD2
RD1
N PACKAGE
(TOP VIEW)
MR
OUT1
DTR
RTS
OUT2
NC
INTRPT
RXRDY
A0
A1
A2
39
38
37
36
35
34
33
32
31
30
29
18 19
7
8
9
10
11
12
13
14
15
16
17
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2
BAUDOUT
20 21 22 23
RI
DCD
DSR
CTS
5 4
3
2
1
6
44
D4
D3
D2
D1
D0
NC
V
RD2
DDIS
TXRDY
ADS
XIN
XOUT
WR1
WR2
NC
RD1
42 41 40
43
24 25 26 27 28
NC No internal connection
CC
V
SS
FN PACKAGE
(TOP VIEW)
14 15
NC
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
NC
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
NC
D5
D6
D7
RCLK
NC
SIN
SOUT
CS0
CS1
CS2
BAUDOUT
17 18 19 20
PT PACKAGE
(TOP VIEW)
RI
DCD
DSR
CTS
47 46 45 44 43
48
42
NC
D4
D3
D2
D1
D0
DDIS
TXRDY
ADS
XOUT
WR1
WR2
RD1
RD2
NC
40 39 38
41
21 22 23 24
37
13
NC
NC
V
CC
XIN
V
SS
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B JANUARY 1994 REVISED AUGUST 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
Receiver
Buffer
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Receiver
FIFO
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Line
Control
Register
Transmitter
FIFO
Interrupt
Enable
Register
Interrupt
I/O
Register
FIFO
Control
Register
Select
and
Control
Logic
Interrupt
Control
Logic
S
e
l
e
c
t
Data
Bus
Buffer
BAUDOUT
SIN
RCLK
SOUT
RTS
CTS
DTR
DSR
DCD
RI
OUT1
OUT2
INTRPT
32
36
33
37
38
39
34
31
30
11
9
10
15
12
A0
28
D7 D0
8 1
Internal
Data Bus
27
26
13
14
25
35
21
22
18
19
23
24
16
17
29
A1
A2
CS0
CS1
CS2
ADS
MR
RD1
RD2
WR1
WR2
DDIS
TXRDY
XIN
XOUT
RXRDY
S
e
l
e
c
t
Receiver
Shift
Register
Receiver
Timing and
Control
Line
Control
Register
Line
Control
Register
Modem
Control
Logic
8
Terminal numbers shown are for the N package.
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B JANUARY 1994 REVISED AUGUST 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
NO.
N
NO.
FN
NO.
PT
I/O
DESCRIPTION
A0
A1
A2
28
27
26
31
30
29
28
27
26
I
Register select. A0 A2 are used during read and write operations to select the ACE register to read
from or write to. Refer to Table 1 for register addresses, and refer to the address strobe (ADS) signal
description.
ADS
25
28
24
I
Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select
signals (CS0, CS1, CS2) drive the internal select logic directly; when high, the register select and chip
select signals are held in the state they are in when the low-to-high transition of ADS occurs.
BAUDOUT
15
17
12
O
Baud out. BAUDOUT is a 16
clock signal for the transmitter section of the ACE. The clock rate is
established by the reference oscillator frequency divided by a divisor specified by the baud generator
divisor latches. BAUDOUT can also be used for the receiver section by tying this output to RCLK.
CS0
CS1
CS2
12
13
14
14
15
16
9
10
11
I
Chip select. When CS0 = high, CS1 = high, and CS2 = low, these three inputs select the ACE. When
any of these inputs are inactive, the ACE remains inactive. Refer to the ADS signal description.
CTS
36
40
38
I
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of
the modem status register. Bit 0 (
CTS) of the modem status register indicates that this signal has
changed states since the last read from the modem status register. If the modem status interrupt is
enabled when CTS changes state, an interrupt is generated.
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
43
44
45
46
47
2
3
4
I/O
Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU.
DCD
38
42
40
I
Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD)
of the modem status register. Bit 3 (
DCD) of the modem status register indicates that this signal has
changed states since the last read from the modem status register. If the modem status interrupt is
enabled when DCD changes state, an interrupt is generated.
DDIS
23
26
22
O
Driver disable. This output is active (high) when the CPU is not reading data. When active, this output
can disable an external transceiver.
DSR
37
41
39
I
Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of
the modem status register. Bit 1 (
DSR) of the modem status register indicates this signal has changed
states since the last read from the modem status register. If the modem status interrupt is enabled when
DSR changes state, an interrupt is generated.
DTR
33
37
33
O
Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to
establish communication. DTR is placed in the active state by setting the DTR bit of the modem control
register to a high level. DTR is placed in the inactive state either as a result of a master reset, during
loop mode operation, or clearing the DTR bit.
INTRPT
30
33
30
O
Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced.
Four conditions that cause an interrupt to be issued are: a receiver error, received data is available or
timed out (FIFO mode only), the transmitter holding register is empty, or an enabled modem status
interrupt. The INTRPT output is reset (deactivated) either when the interrupt is serviced or as a result
of a master reset.
MR
35
39
35
I
Master reset. When active (high), MR clears most ACE registers and sets the state of various output
signals. Refer to Table 2.
OUT1
OUT2
34
31
38
35
34
31
O
Outputs 1 and 2. User-designated outputs that are set to their active low states by setting their
respective modem control register bits (OUT1 and OUT2) high. OUT1 and OUT2 are set to their inactive
(high) states as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or
bit 3 (OUT2) of the modem control register.
RCLK
9
10
5
I
Receiver clock. RCLK is the 16
baud rate clock for the receiver section of the ACE.
PDF 
ZIP