TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Programmable Auto-RTS and Auto-CTS

In Auto-CTS Mode, CTS Controls
Transmitter

In Auto-RTS Mode, RCV FIFO Contents and
Threshold Control RTS

Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on
the Same Power Drop

Capable of Running With All Existing
TL16C450 Software

After Reset, All Registers Are Identical to
the TL16C450 Register Set

Up to 24-MHz Clock Rate for up to
1.5-Mbaud Operation With V

= 5 V

Up to 20-MHz Clock Rate for up to
1.25-Mbaud Operation With V

= 3.3 V

Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation With V

= 2.5 V

In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data

Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2

-1) and Generates an Internal 16

Clock

Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream

5-V, 3.3-V, and 2.5-V Operation

Independent Receiver Clock Input

Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled

Fully Programmable Serial Interface
Characteristics:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit Generation

and Detection

- 1-, 1 1/2-, or 2-Stop Bit Generation
- Baud Generation (dc to 1 Mbit/s)

False-Start Bit Detection

Complete Status Reporting Capabilities

3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus

Line Break Generation and Detection

Internal Diagnostic Capabilities:
- Loopback Controls for Communications

Link Fault Isolation

- Break, Parity, Overrun, and Framing

Error Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)

Available in 48-Pin PT, 48-Pin PFB, and
32-Pin RHB Packages

description

The TL16C550D and the TL16C550DI are speed and operating voltage upgrades (but functional equivalents)
of the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the
TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the
TL16C550D and the TL16C550DI, like the TL16C550C, can be placed in an alternate FIFO mode. This relieves
the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and
transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver
FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software
overload and increase system efficiency by automatically controlling serial data flow using RTS output and CTS
input signals.

The TL16C550D and TL16C550DI perform serial-to-parallel conversions on data received from a peripheral
device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE
status at any time. The ACE includes complete modem control capability and a processor interrupt system that
can be tailored to minimize software management of the communications link.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

2004 - 2005, Texas Instruments Incorporated

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Both the TL16C550D and the TL16C550DI ACE include a programmable baud rate generator capable of
dividing a reference clock by divisors from 1 to 65535 and producing a 16

reference clock for the internal

transmitter logic. Provisions are included to use this 16

clock for the receiver logic. The ACE accommodates

up to a 1.5-Mbaud serial rate (24-MHz input clock) so that a bit time is 667 ns and a typical character time is
6.7

s (start bit, 8 data bits, stop bit).

Two of the TL16C450 terminal functions on the TL16C550D and the TL16C550DI have been changed to
TXRDY and RXRDY, which provide signaling to a DMA controller.

NC - No internal connection

14 15

NC
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
NC

D5
D6
D7

RCLK

SIN

SOUT

CS0
CS1
CS2

BAUDOUT

17 18 19 20

PT/PFB PACKAGE

(TOP VIEW)

DCD

DSR

CTS

47 46 45 44 43

DDIS

TXRDY

ADS

XOUT

WR1

WR2

RD1

RD2

40 39 38

21 22 23 24

XIN

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

RHB PACKAGE

(TOP VIEW)

23 22 21 20 19

1 2

NC
NC
RD1
V

WR1
XOUT
XIN
NC

DSR

DCD

D0
D1
D2
D3

5 6 7

CTS

DTR

INTRPT

SIN

SOUT

CS2

NC - No internal connection

The TL16C550D is being made available in a reduced pin count package, the 32-pin RHB package. This is
accomplished by eliminating some signals that are not required for some applications. These include the CS0,
CS1, ADS, RD2, WR2, and RCLK input signals and the DDIS, TXRDY, RXRDY, OUT1, OUT2, and BAUDOUT
output signals. There is an internal connection between BAUDOUT and RCLK.

All of the functionality of the TL16C550D is maintained in the RHB package.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

detailed description

autoflow control (see Figure 1)

Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before
the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data
and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless
the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a
TLC16C550D with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds
the receiver FIFO read latency.

RCV

FIFO

Serial to

Parallel

Flow

Control

XMT

FIFO

Parallel

to Serial

Flow

Control

Parallel

to Serial

Flow

Control

Serial to

Parallel

Flow

Control

XMT

FIFO

RCV

FIFO

ACE1

ACE2

D7 - D0

SIN

SOUT

RTS

CTS

SOUT

SIN

CTS

RTS

D7 - D0

Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example

auto-RTS (see Figure 1)

Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram)
and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level
of 1, 4, or 8 (see Figure 3), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send
an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send)
because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS
is automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.

When the trigger level is 14 (see Figure 4), RTS is deasserted after the first data bit of the 16th character is
present on the SIN line. RTS is reasserted when the RCV FIFO has at least one available byte space.

auto-CTS (see Figure 1)

The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the
last stop bit that is currently being sent (see Figure 2). The auto-CTS function reduces interrupts to the host
system. When flow control is enabled, CTS level changes do not trigger host interrupts because the device
automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the
transmit FIFO and a receiver overrun error may result.

enabling autoflow control and auto-CTS

Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to
a 1. Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem
control register must be cleared (this assumes that a control signal is driving CTS).

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

auto-CTS and auto-RTS functional timing

Start

Bits 0 - 7

Start

Bits 0 - 7

Start

Bits 0 - 7

Stop

SOUT

CTS

NOTES: A. When CTS is low, the transmitter keeps sending serial data out.

B. If CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does

not send the next byte.

C. When CTS goes from high to low, the transmitter begins sending data again.

Figure 2. CTS Functional Timing Waveforms

The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.

Start

Byte N

Start

Byte N+1

Start

Byte

Stop

SIN

RTS

RD1

(RD RBR)

N+1

NOTES: A. N = RCV FIFO trigger level (1, 4, or 8 bytes)

B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS section.

Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes

Byte 14

Byte 15

SIN

RTS

RD1

(RD RBR)

Start

Byte 18 Stop

Start

Byte 16

Stop

RTS Released After the

First Data Bit of Byte 16

NOTES: A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the

sixteenth byte.

B. RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more than

one byte of space available.

C. When the receive FIFO is full, the first receive buffer register read reasserts RTS.

Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

functional block diagram (for PT and PFB packages)

Receiver

Buffer

Register

Divisor

Latch (LS)

Divisor

Latch (MS)

Baud

Generator

Receiver

FIFO

Line

Status

Register

Transmitter

Holding

Register

Modem

Control

Register

Modem

Status

Register

Line

Control

Register

Transmitter

FIFO

Interrupt

Enable

Register

Interrupt

Identification

Register

FIFO

Control

Register

Select

and

Control

Logic

Interrupt

Control

Logic

S
e

e
c

Data

Bus

Buffer

BAUDOUT

SIN

RCLK

SOUT

CTS

DTR

DSR

DCD

OUT1

OUT2

INTRPT

D(7 - 0)

4 -2
47-43

Internal
Data Bus

CS0

CS1

CS2

ADS

RD1

RD2

WR1

WR2

DDIS

TXRDY

XIN

XOUT

RXRDY

S
e

e
c

Receiver

Shift

Register

Receiver

Timing and

Control

Transmitter

Timing and

Control

Transmitter

Shift

Register

Modem

Control

Logic

Power
Supply

RTS

Autoflow
Control
(AFE)

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

functional block diagram (for RHB package)

Receiver

Buffer

Register

Divisor

Latch (LS)

Divisor

Latch (MS)

Baud

Generator

Receiver

FIFO

Line

Status

Register

Transmitter

Holding

Register

Modem

Control

Register

Modem

Status

Register

Line

Control

Register

Transmitter

FIFO

Interrupt

Enable

Register

Interrupt

Identification

Register

FIFO

Control

Register

Select

and

Control

Logic

Interrupt

Control

Logic

S
e

e
c

Data

Bus

Buffer

SIN

SOUT

CTS

DTR

DSR

DCD

INTRPT

D(7 - 0)

5-3, 1
32-29

Internal
Data Bus

CS2

RD1

WR1

XIN

XOUT

S
e

e
c

Receiver

Shift

Register

Receiver

Timing and

Control

Transmitter

Timing and

Control

Transmitter

Shift

Register

Modem

Control

Logic

Power
Supply

RTS

Autoflow
Control
(AFE)

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions (for PT and PFB packages)

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

A0
A1
A2

28
27
26

Register select. A0 - A2 are used during read and write operations to select the ACE register to read from or
write to. See Table 1 for register addresses, and see the ADS description.

ADS

Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1, and CS2 drive the internal select
logic directly; when ADS is high, the register select and chip select signals are held at the logic levels they were
in when the low-to-high transition of ADS occurred.

BAUDOUT

Baud out. BAUDOUT is a 16

clock signal for the transmitter section of the ACE. The clock rate is established

by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches.
BAUDOUT may also be used for the receiver section by tying this output to RCLK.

CS0
CS1
CS2

Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs select the ACE. When any of these
inputs are inactive, the ACE remains inactive (see the ADS description).

CTS

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem
status register. Bit 0 (

CTS) of the modem status register indicates that CTS has changed states since the

last read from the modem status register. If the modem status interrupt is enabled when CTS changes levels
and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to
control the transmitter.

D0
D1
D2
D3
D4
D5
D6
D7

43
44
45
46
47

2
3
4

I/O

Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU.

DCD

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (

DCD) of the modem status register indicates that DCD has changed states

since the last read from the modem status register. If the modem status interrupt is enabled when DCD
changes levels, an interrupt is generated.

DDIS

Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable an
external transceiver.

DSR

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the
modem status register. Bit 1 (

DSR) of the modem status register indicates DSR has changed levels since

the last read from the modem status register. If the modem status interrupt is enabled when DSR changes
levels, an interrupt is generated.

DTR

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR is placed in the active level by setting the DTR bit of the modem control register. DTR
is placed in the inactive level either as a result of a master reset, during loop mode operation, or clearing the
DTR bit.

INTRPT

Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four
conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed
out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT
is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.

Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals
(see Table 2).

1, 6, 13,

21, 25, 36,

37, 48

No connection

OUT1
OUT2

34
31

Outputs 1 and 2. These are user-designated output terminals that are set to the active (low) level by setting
respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to inactive the
(high) level as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2)
of the MCR.

RCLK

Receiver clock. RCLK is the 16

baud rate clock for the receiver section of the ACE.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions (for PT and PFB packages) (continued)

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

RD1
RD2

19
20

Read inputs. When either RD1 or RD2 is active (low or high, respectively) while the ACE is selected, the CPU
is allowed to read status information or data from a selected ACE register. Only one of these inputs is required
for the transfer of data during a read operation; the other input must be tied to its inactive level (i.e., RD2 tied
low or RD1 tied high).

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem
status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from a low to a high
level since the last read from the modem status register. If the modem status interrupt is enabled when this
transition occurs, an interrupt is generated.

RTS

Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS
is set to the active level by setting the RTS modem control register bit and is set to the inactive (high) level either
as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In the
auto-RTS mode, RTS is set to the inactive level by the receiver threshold control logic.

RXRDY

Receiver ready. Receiver direct memory access (DMA) signalling is available with RXRDY. When operating
in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO control register bit 3
(FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer
DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which
multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0
or FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiver holding register,
RXRDY is active (low). When RXRDY has been active but there are no characters in the FIFO or holding
register, RXRDY goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level or the
time-out has been reached, RXRDY goes active (low); when it has been active but there are no more
characters in the FIFO or holding register, it goes inactive (high).

SIN

Serial data input. SIN is serial data input from a connected communications device

SOUT

Serial data output. SOUT is composite serial data output to a connected communication device. SOUT is set
to the marking (high) level as a result of master reset.

TXRDY

Transmitter ready. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO mode,
one of two types of DMA signalling can be selected using FCR3. When operating in the TL16C450 mode, only
DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus
cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit
FIFO has been filled.

2.25-V to 5.5-V power supply voltage

Supply common

WR1
WR2

16
17

Write inputs. When either WR1 or WR2 is active (low or high, respectively) and while the ACE is selected, the
CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required
to transfer data during a write operation; the other input must be tied to its inactive level (i.e., WR2 tied low or
WR1 tied high).

XIN
XOUT

14
15

I/O

External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions (for RHB package)

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

A0
A1
A2

19
18
17

Register select. A0 - A2 are used during read and write operations to select the ACE register to read from or
write to. See Table 1 for register addresses, and see the ADS description.

CS2

Chip select. When CS2 is low, the ACE is selected. When CS2 is high, the ACE remains inactive.

CTS

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem
status register. Bit 0 (

CTS) of the modem status register indicates that CTS has changed states since the

D0
D1
D2
D3
D4
D5
D6
D7

29
30
31
32

1
3
4
5

I/O

Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU.

DCD

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (

DCD) of the modem status register indicates that DCD has changed states

since the last read from the modem status register. If the modem status interrupt is enabled when DCD
changes levels, an interrupt is generated.

DSR

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the
modem status register. Bit 1 (

DSR) of the modem status register indicates DSR has changed levels since

the last read from the modem status register. If the modem status interrupt is enabled when DSR changes
levels, an interrupt is generated.

DTR

INTRPT

Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals
(see Table 2).

2, 9,

15, 16

No connection

RD1

Read input. When RD1 is active (low) while the ACE is selected, the CPU is allowed to read status information
or data from a selected ACE register.

RTS

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

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Terminal Functions (for RHB package) (continued)

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

SIN

Serial data input. SIN is serial data input from a connected communications device

SOUT

Serial data output. SOUT is composite serial data output to a connected communication device. SOUT is set
to the marking (high) level as a result of master reset.

2.25-V to 5.5-V power supply

Supply common, ground

WR1

Write input. When WR1 is active (low) while the ACE is selected, the CPU is allowed to write control words
or data into a selected ACE register.

XIN
XOUT

External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 1)

-0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range at any input, V

-0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

-0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

, TL16C550D

C to 70

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TL16C550DI

-40

C to 85

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

-65

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: PT and PFB packages

260

. . . . . . . . . .

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

recommended operating conditions

2.5 V

10%

MIN

NOM

MAX

UNIT

Supply voltage, V

2.25

2.5

2.75

Input voltage, V

High-level input voltage, V

1.8

2.75

Low-level input voltage, V

-0.3

0.6

Output voltage, V

High-level output current, I

(all outputs)

Low-level output current, I

(all outputs)

Oscillator/clock speed

MHz

3.3 V

10%

MIN

NOM

MAX

UNIT

Supply voltage, V

3.3

3.6

Input voltage, V

High-level input voltage, V

0.7 V

Low-level input voltage, V

0.3 V

Output voltage, V

High-level output current, I

(all outputs)

1.8

Low-level output current, I

(all outputs)

3.2

Oscillator/clock speed

MHz

5 V

10%

MIN

NOM

MAX

UNIT

Supply voltage, V

4.5

5.5

Input voltage, V

Except XIN

High-level input voltage, V

XIN

0.7 V

Except XIN

0.8

Low-level input voltage, V

XIN

0.3 V

Output voltage, V

High-level output current, I

(all outputs)

Low-level output current, I

(all outputs)

Oscillator/clock speed

MHz

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

2.5 V nominal

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

High-level output voltage

= - 1 mA

1.8

Low-level output voltage

= 2 mA

0.5

= 3.6 V,

= 0,

Input current

= 3.6 V,

= 0 to 3.6 V,

= 0,

All other terminals floating

= 3.6 V,

= 0,

High-impedance-state output current

= 3.6 V,

= 0,

= 0 to 3.6 V,

High-impedance-state output current

= 0 to 3.6 V,

Chip selected in write mode or chip deselect

= 3.6 V,

= 25

Supply current

SIN, DSR, DCD, CTS, and RI at 2 V,

Supply current

All other inputs at 0.8 V,

XTAL1 at 4 MHz,

No load on outputs,

Baud rate = 50 kbit/s

i(CLK)

Clock input capacitance

o(CLK)

Clock output capacitance

= 0,

Input capacitance

f = 1 MHz,

= 25

All other terminals grounded

Output capacitance

All other terminals grounded

All typical values are at V

= 2.5 V and T

= 25

These parameters apply for all outputs except XOUT.

3.3 V nominal

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

High-level output voltage

= - 1.8 mA

2.4

Low-level output voltage

= 3.2 mA

0.5

= 3.6 V,

= 0,

Input current

= 3.6 V,

= 0 to 3.6 V,

= 0,

All other terminals floating

= 3.6 V,

= 0,

High-impedance-state output current

= 3.6 V,

= 0,

= 0 to 3.6 V,

High-impedance-state output current

= 0 to 3.6 V,

Chip selected in write mode or chip deselect

= 3.6 V,

= 25

Supply current

SIN, DSR, DCD, CTS, and RI at 2 V,

Supply current

All other inputs at 0.8 V,

XTAL1 at 4 MHz,

No load on outputs,

Baud rate = 50 kbit/s

i(CLK)

Clock input capacitance

o(CLK)

Clock output capacitance

= 0,

Input capacitance

f = 1 MHz,

= 25

All other terminals grounded

Output capacitance

All other terminals grounded

All typical values are at V

= 3.3 V and T

= 25

These parameters apply for all outputs except XOUT.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)

5 V nominal

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

High-level output voltage

= -4 mA

4.0

Low-level output voltage

= 4 mA

0.4

= 5.25 V,

= 0,

Input current

= 5.25 V,

= 0 to 5.25 V,

= 0,

All other terminals floating

= 5.25 V,

= 0,

High-impedance-state output current

= 5.25 V,

= 0,

= 0 to 5.25 V,

High-impedance-state output current

= 0 to 5.25 V,

Chip selected in write mode or chip deselect

= 5.25 V,

= 25

Supply current

SIN, DSR, DCD, CTS, and RI at 2 V,

Supply current

All other inputs at 0.8 V,

XTAL1 at 4 MHz,

No load on outputs,

Baud rate = 50 kbit/s

i(CLK)

Clock input capacitance

o(CLK)

Clock output capacitance

= 0,

Input capacitance

f = 1 MHz,

= 25

All other terminals grounded

Output capacitance

All other terminals grounded

All typical values are at V

= 5 V and T

= 25

These parameters apply for all outputs except XOUT.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

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system timing requirements over recommended ranges of supply voltage and operating free-air
temperature

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

Cycle time, read (t

+ t

)

Cycle time, write (t

+ t

)

Pulse duration, clock high

f = 16 MHz Max,

Pulse duration, clock low

f = 16 MHz Max,
V

= 2.5 V

Pulse duration, clock high

f = 20 MHz Max,

Pulse duration, clock low

f = 20 MHz Max,
V

= 3.3 V

Pulse duration, clock high

f = 24 MHz Max,

Pulse duration, clock low

f = 24 MHz Max,
V

= 5 V

Pulse duration, ADS low

ADS

6, 7

Pulse duration, WR

Pulse duration, RD

Pulse duration, MR

su1

Setup time, address valid before ADS

su2

Setup time, CS valid before ADS

6, 7

su3

Setup time, data valid before WR1

or WR2

su4

Setup time, CTS

before midpoint of stop bit

Hold time, address low after ADS

Hold time, CS valid after ADS

6, 7

Hold time, CS valid after WR1

or WR2

WCS

Hold time, address valid after WR1

or WR2

Hold time, data valid after WR1

or WR2

Hold time, CS valid after RD1

or RD2

RCS

Hold time, address valid after RD1

or RD2

Delay time, CS valid before WR1

or WR2

CSW

Delay time, address valid before WR1

or WR2

Delay time, write cycle, WR1

or WR2

to ADS

Delay time, CS valid to RD1

or RD2

CSR

Delay time, address valid to RD1

or RD2

Delay time, read cycle, RD1

or RD2

to ADS

tRC

d10

Delay time, RD1

or RD2

to data valid

RVD

= 75 pF

d11

Delay time, RD1

or RD2

to floating data

= 75 pF

Only applies when ADS is low

system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 2)

PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

dis(R)

Disable time, RD1

or RD2

to DDIS

RDD

= 75 pF

NOTE 2: Charge and discharge times are determined by V

, V

, and external loading.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

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baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, C

= 75 pF (for PT and PFB packages only)

PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

Pulse duration, BAUDOUT low

f = 24 MHz, CLK

Pulse duration, BAUDOUT high

f = 24 MHz, CLK

= 5 V

Delay time, XIN

to BAUDOUT

BLD

Delay time, XIN

to BAUDOUT

BHD

receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 3)

PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

d12

Delay time, RCLK to sample

SCD

d13

Delay time, stop to set INTRPT or read
RBR to LSI interrupt or stop to RXRDY

SINT

8, 9, 10,

11, 12

RCLK

cycle

d14

Delay time, read RBR/LSR to reset INTRPT

RINT

8, 9, 10,

11, 12

= 75 pF

NOTE 3: In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt identification

transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature

PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

d15

Delay time, initial write to transmit start

IRS

baudout

cycles

d16

Delay time, start to INTRPT

STI

baudout

cycles

d17

Delay time, WR1 (WR THR) to reset INTRPT

= 75 pF

d18

Delay time, initial write to INTRPT (THRE

)

baudout

cycles

d19

Delay time, read IIR

to reset INTRPT

(THRE

)

= 75 pF

d20

Delay time, write to TXRDY inactive

WXI

14,15

= 75 pF

d21

Delay time, start to TXRDY active

SXA

14,15

= 75 pF

baudout

cycles

THRE = transmitter holding register empty; IIR = interrupt identification register.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

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modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, C

= 75 pF

PARAMETER

ALT. SYMBOL

FIGURE

MIN

MAX

UNIT

d22

Delay time, WR2 MCR to output

MDO

d23

Delay time, modem interrupt to set INTRPT

SIM

d24

Delay time, RD2 MSR to reset INTRPT

RIM

d25

Delay time, CTS low to SOUT

baudout

cycles

d26

Delay time, RCV threshold byte to RTS

baudout

cycles

d27

Delay time, read of last byte in receive FIFO to RTS

baudout

cycles

d28

Delay time, first data bit of 16th character to RTS

baudout

cycles

d29

Delay time, RBRRD low to RTS

baudout

cycles

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

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PARAMETER MEASUREMENT INFORMATION

d13

(see Note A)

d14

Stop

Top Byte of FIFO

Sample Clock

SIN

Time-Out or

Trigger Level

Interrupt

Line Status

Interrupt (LSI)

d13

(FIFO at or above
trigger level)

(FIFO below
trigger level)

RD1, RD2

(RD LSR)

RD1, RD2

(RD RBR)

Active

d14

Previous Byte

Read From FIFO

50%

The RD2 signal is applicable only to the PT and PFB packages.

NOTE A: For a time-out interrupt, t

d13

= 9 RCLKs.

Figure 10. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms

d13

(see Note B)

d14

Stop

Sample Clock

SIN

(first byte)

Active

RD1

(RD RBR)

RXRDY

See Note A

50%

The RXRDY signal is applicable only to the PT and PFB packages.

NOTES: A. This is the reading of the last byte in the FIFO.

B. For a time-out interrupt, t

d13

= 9 RCLKs.

Figure 11. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

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PARAMETER MEASUREMENT INFORMATION

d13

(see Note B)

d14

Sample Clock

SIN

(first byte that reaches

the trigger level)

Active

RD1

(RD RBR)

RXRDY

See Note A

50%

The RXRDY signal is applicable only to the PT and PFB packages.

NOTES: A. This is the reading of the last byte in the FIFO.

B. For a time-out interrupt, t

d13

= 9 RCLKs.

Figure 12. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)

d16

Parity

Stop

Start

Data Bits

SOUT

Start

d15

d17

d18

d19

INTRPT

(THRE)

WR1

(WR THR)

RD IIR

50%

Figure 13. Transmitter Timing Waveforms

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

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PARAMETER MEASUREMENT INFORMATION

d20

WR1

(WR THR)

d21

Parity

Stop

Data

Start

Byte 1

SOUT

TXRDY

50%

The TXRDY signal is applicable only to the PT and PFB packages.

Figure 14. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)

WR1

(WR THR)

Parity

Stop

Data

Start

Byte 16

SOUT

TXRDY

FIFO Full

d20

d21

50%

The TXRDY signal is applicable only to the PT and PFB packages.

Figure 15. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

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PARAMETER MEASUREMENT INFORMATION

WR2

(WR MCR)

RTS, DTR,

OUT1

, OUT2

CTS, DSR, DCD

d23

d24

d23

INTRPT

(modem)

RD2

(RD MSR)

50%

d22

The OUT1, OUT2, RD2, and WR2 signals are applicable only to the PT and PFB packages.

Figure 16. Modem Control Timing Waveforms

Midpoint of Stop Bit

d25

su4

CTS

SOUT

50%

Figure 17. CTS and SOUT Autoflow Control Timing (Start and Stop) Waveforms

d27

SIN

50%

d26

50%

Midpoint of Stop Bit

RTS

RBRRD

Figure 18. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

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PARAMETER MEASUREMENT INFORMATION

SIN

50%

d28

50%

Midpoint of Data Bit 0

RTS

RBRRD

15th Character

16th Character

d29

Figure 19. Auto-RTS Timing for RCV Threshold of 14 Waveforms

APPLICATION INFORMATION

D7 - D0

MEMR or I/OR

MEMW or I/ON

INTR

RESET

EIA-232-D

Drivers

and Receivers

XOUT

XIN

RCLK

BAUDOUT

CTS

DCD

DSR

DTR

RTS

SOUT

SIN

INTRPT

D7 - D0

RD1

WR1

ADS

WR2

RD2

CS2

CS1

CS0

TL16C550D

(ACE)

3.072 MHz

C
P
U

B
u
s

Figure 20. Basic TL16C550D Configuration (for PT and PFB Packages)

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

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APPLICATION INFORMATION

D7 - D0

MEMR or I/OR

MEMW or I/ON

INTR

RESET

EIA-232-D

Drivers

and Receivers

XOUT

XIN

CTS

DCD

DSR

DTR

RTS

SOUT

SIN

INTRPT

D7 - D0

RD1

WR1

CS2

TL16C550D

(ACE)

3.072 MHz

C
P
U

B
u
s

Figure 21. Basic TL16C550D Configuration (for RHB Package)

Receiver Disable

Microcomputer

System

Data Bus

Driver Disable

8-Bit

Bus Transceiver

WR1

D7 - D0

DDIS

TL16C550D

(ACE)

Figure 22. Typical Interface for a High Capacity Data Bus

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

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APPLICATION INFORMATION

Buffer

Address
Decoder

A16 - A23

ADS

AD0 - AD15

RSI/ABT

PHI1

PHI2

PHI1

PHI2

ADS

CPU

RSTO

A16 - A23

CS0

CS1

CS2

A0 - A2

D0 - D7

AD0 - AD7

RD1

WR1

AD0 - AD15

RD2

WR2

XIN

XOUT

BAUDOUT

RCLK

DTR

RTS

OUT1

OUT2

DCD

DSR

CTS

SIN

SOUT

INTRPT

TXRDY

DDIS

RXRDY

GND
(V

)

Alternate

Crystal Control

TL16C550D

EIA-232-D
Connector

TCU

Figure 23. Typical TL16C550D Connection to a CPU (for PT and PFB Packages)

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

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PRINCIPLES OF OPERATION

Table 1. Register Selection

DLAB

REGISTER

Receiver buffer (read), transmitter holding register (write)

Interrupt enable register

Interrupt identification register (read only)

FIFO control register (write)

Line control register

Modem control register

Line status register

Modem status register

Scratch register

Divisor latch (LSB)

Divisor latch (MSB)

The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal
is controlled by writing to this bit location (see Table 4).

Table 2. ACE Reset Functions

REGISTER/SIGNAL

RESET CONTROL

RESET STATE

Interrupt enable register

Master reset

All bits cleared (0 - 3 forced and 4 - 7 permanent)

Interrupt identification register

Master reset

Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits 4 - 5 are
permanently cleared

FIFO control register

Master reset

All bits cleared

Line control register

Master reset

All bits cleared

Modem control register

Master reset

All bits cleared (6 - 7 permanent)

Line status register

Master reset

Bits 5 and 6 are set; all other bits are cleared

Modem status register

Master reset

Bits 0 - 3 are cleared; bits 4 - 7 are input signals

SOUT

Master reset

High

INTRPT (receiver error flag)

Read LSR/MR

Low

INTRPT (received data available)

Read RBR/MR

Low

INTRPT (transmitter holding register empty)

Read IR/write THR/MR

Low

INTRPT (modem status changes)

Read MSR/MR

Low

OUT2

Master reset

High

RTS

Master reset

High

DTR

Master reset

High

OUT1

Master reset

High

Scratch register

Master reset

No effect

Divisor latch (LSB and MSB) registers

Master reset

No effect

Receiver buffer register

Master reset

No effect

Transmitter holding register

Master reset

No effect

RCVR FIFO

MR/FCR1 - FCR0/

FCR0

All bits cleared

XMIT FIFO

MR/FCR2 - FCR0/

FCR0

All bits cleared

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

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PRINCIPLES OF OPERATION

accessible registers

The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.

Table 3. Summary of Accessible Registers

REGISTER ADDRESS

0 DLAB = 0

1 DLAB = 0

0 DLAB = 1

1 DLAB = 1

BIT

NO.

Receiver

Buffer

Register

(Read

Only)

Transmitter

Holding

Register

(Write

Only)

Interrupt

Enable

Register

Interrupt

Ident.

Register

(Read

Only)

FIFO

Control

Register

(Write

Only)

Line

Control

Register

Modem

Control

Register

Line

Status

Register

Modem

Status

Register

Scratch

Register

Divisor

Latch
(LSB)

Latch

(MSB)

RBR

THR

IER

IIR

FCR

LCR

MCR

LSR

MSR

SCR

DLL

DLM

Data Bit 0

Enable

Received

Data

Available

Interrupt

(ERBI)

0 if

Interrupt
Pending

FIFO

Enable

Word

Length

Select

Bit 0

(WLS0)

Data

Terminal

Ready

(DTR)

Data

Ready

(DR)

Delta
Clear

to Send

(

CTS)

Bit 0

Bit 8

Data Bit 1

Enable

Transmitter

Holding

Empty

Interrupt

(ETBEI)

Interrupt

Bit 1

Receiver

FIFO

Reset

Word

Length

Select

Bit 1

(WLS1)

Request

to Send

(RTS)

Overrun

Error

(OE)

Delta
Data

Set

Ready

(

DSR)

Bit 1

Bit 9

Data Bit 2

Enable

Receiver

Line Status

Interrupt

(ELSI)

Interrupt

Bit 2

Transmitter

FIFO

Reset

Number

Stop Bits

(STB)

OUT1

Parity

Error

(PE)

Trailing

Edge Ring

Indicator

(TERI)

Bit 2

Bit 10

Data Bit 3

Enable

Modem

Status

Interrupt
(EDSSI)

Interrupt

Bit 3
(see

Note 4)

DMA

Mode

Select

Parity

Enable

(PEN)

OUT2

Framing

Error

(FE)

Delta
Data

Carrier

Detect

(

DCD)

Bit 3

Bit 11

Data Bit 4

Reserved

Even
Parity

Select

(EPS)

Loop

Break

Interrupt

(BI)

Clear

Send

(CTS)

Bit 4

Bit 12

Data Bit 5

Reserved

Stick

Parity

Autoflow

Control

Enable

(AFE)

Transmitter

Holding

(THRE)

Data

Set

Ready

(DSR)

Bit 5

Bit 13

Data Bit 6

FIFOs

Enabled

(see

Note 4)

Receiver

Trigger

(LSB)

Break

Control

Transmitter

Empty

(TEMT)

Ring

Indicator

(RI)

Bit 6

Bit 14

Data Bit 7

FIFOs

Enabled

(see

Note 4)

Receiver

Trigger

(MSB)

Divisor

Latch

Access

Bit

(DLAB)

Error in

RCVR

FIFO

(see

Note 4)

Data

Carrier

Detect
(DCD)

Bit 7

Bit 15

Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

NOTE 4: These bits are always 0 in the TL16C450 mode.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

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PRINCIPLES OF OPERATION

FIFO control register (FCR)

The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.

Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR
bits are written to or they are not programmed. Changing this bit clears the FIFOs.

Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.

Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.

Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.

Bits 4 and 5: These two bits are reserved for future use.

Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 4).

Table 4. Receiver FIFO Trigger Level

BIT 7

BIT 6

RECEIVER FIFO

TRIGGER LEVEL (BYTES)

FIFO interrupt mode operation

When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt
occurs as follows:

The received data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.

The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt, it is cleared when the FIFO drops below the trigger level.

The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04)
interrupt.

The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO.
It is cleared when the FIFO is empty.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

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PRINCIPLES OF OPERATION

FIFO interrupt mode operation (continued)

When the receiver FIFO and receiver interrupts are enabled:

FIFO time-out interrupt occurs if the following conditions exist:

At least one character is in the FIFO.

The most recent serial character was received more than four continuous character times ago (if two
stop bits are programmed, the second one is included in this time delay).

The most recent microprocessor read of the FIFO has occurred more than four continuous character
times before. This causes a maximum character received command to interrupt an issued delay of
160 ms at a 300-baud rate with a 12-bit character.

Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional
to the baud rate).

When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads
one character from the receiver FIFO.

When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received
or after the microprocessor reads the receiver FIFO.

When the transmitter FIFO and THRE interrupts are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur
as follows:

The transmitter-holding-register-empty interrupt [IIR (3 -0) = 2] occurs when the transmit FIFO is empty. It
is cleared [IIR (3-0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO
while servicing this interrupt) or the IIR is read.

The transmitter-holding-register-empty interrupt is delayed one character time minus the last stop bit time
when there have not been at least two bytes in the transmitter FIFO at the same time since the last time
that the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.

FIFO-polled mode operation

With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts
the ACE in the FIFO-polled mode of operation. Because the receiver and transmitter are controlled separately,
either one or both can be in the polled mode of operation.

In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:

LSR0 is set as long as one byte is in the receiver FIFO.

LSR1 through LSR4 specify which error(s) have occurred. Character error status is handled the same way
as when in the interrupt mode; the IIR is not affected since IER2 = 0.

LSR5 indicates when the THR is empty.

LSR6 indicates that both the THR and TSR are empty.

LSR7 indicates whether any errors are in the receiver FIFO.

There is no trigger level reached or time-out condition indicated in the FIFO-polled mode. However, the receiver
and transmitter FIFOs are still fully capable of holding characters.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

interrupt enable register (IER)

The IER enables each of the five types of interrupts (see Table 5) and enables INTRPT in response to an
interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents
of this register are summarized in Table 3 and are described in the following bullets.

Bit 0: When set, this bit enables the received data available interrupt.

Bit 1: When set, this bit enables the THRE interrupt.

Bit 2: When set, this bit enables the receiver line status interrupt.

Bit 3: When set, this bit enables the modem status interrupt.

Bits 4 through 7: These bits are not used (always cleared).

interrupt identification register (IIR)

The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
the most popular microprocessors.

The ACE provides four prioritized levels of interrupts:

Priority 1 - Receiver line status (highest priority)

Priority 2 - Receiver data ready or receiver character time-out

Priority 3 - Transmitter holding register empty

Priority 4 - Modem status (lowest priority)

When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt
in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and
described in Table 5. Detail on each bit is as follows:

Bit 0: This bit is used either in a hardwire-prioritized or polled-interrupt system. When bit 0 is cleared, an
interrupt is pending. If bit 0 is set, no interrupt is pending.

Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3

Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a
time-out interrupt is pending.

Bits 4 and 5: These two bits are not used (always cleared).

Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control
register is set.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

interrupt identification register (IIR) (continued)

Table 5. Interrupt Control Functions

INTERRUPT

IDENTIFICATION REGISTER

PRIORITY

INTERRUPT TYPE

INTERRUPT SOURCE

INTERRUPT RESET

BIT 3

BIT 2

BIT 1

BIT 0

LEVEL

INTERRUPT TYPE

INTERRUPT SOURCE

METHOD

None

Receiver line status

Overrun error, parity error,
framing error, or break interrupt

Read the line status register

Received data available

Receiver data available in the
TL16C450 mode or trigger level
reached in the FIFO mode

Read the receiver buffer register

Character time-out
indication

No characters have been
removed from or input to the
receiver FIFO during the last four
character times, and there is at
least one character in it during
this time

Read the receiver buffer register

Transmitter holding
register empty

Transmitter holding register
empty

Read the interrupt identification
register (if source of interrupt) or
writing into the transmitter
holding register

Modem status

Clear to send, data set ready,
ring indicator, or data carrier
detect

Read the modem status register

line control register (LCR)

The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and described in the following bulleted list.

Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 6.

Table 6. Serial Character Word Length

BIT 1

BIT 0

WORD LENGTH

5 bits

6 bits

7 bits

8 bits

Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit
regardless of the number of stop bits selected. The number of stop bits generated in relation to word length
and bit 2 are shown in Table 7.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

line control register (LCR) (continued)

Table 7. Number of Stop Bits Generated

BIT 2

WORD LENGTH SELECTED

BY BITS 1 AND 2

NUMBER OF STOP

BITS GENERATED

Any word length

5 bits

1 1/2

6 bits

7 bits

8 bits

Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.

Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is
cleared, odd parity (an odd number of logic 1s) is selected.

Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked
as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set.
If bit 5 is cleared, stick parity is disabled.

Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT
is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no
effect on the transmitter logic; it only effects SOUT.

Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver
buffer, the THR, or the IER.

line status register (LSR)

The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 3 and described in the following bulleted list.

Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the
data in the RBR or the FIFO.

Bit 1

: This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in

the RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every
time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the
trigger level, an overrun error occurs only after the FIFO is full, and the next character has been completely
received in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character
in the shift register is overwritten, but it is not transferred to the FIFO.

The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.

Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

line status register (LSR) (continued)

Bit 2

: This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received

data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads
the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO
to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.

Bit 3

: This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character

did not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the
FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error
is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to
resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the
next start bit. The ACE samples this start bit twice and then accepts the input data.

Bit 4

: This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input

was held low for longer than a full-word transmission time. A full-word transmission time is defined as the
total time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU reads the contents
of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it
applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a
break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after SIN
goes to the marking state for at least two RCLK samples and then receives the next valid start bit.

Bit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the ACE is ready
to accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated.
THRE is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the
loading of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared
when at least one byte is written to the transmit FIFO.

Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are
both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,
TEMT is set when the transmitter FIFO and shift register are both empty.

Bit 7: In the TL16C550D mode, this bit is always cleared. In the TL16C450 mode, this bit is always cleared.
In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is
cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO.

modem control register (MCR)

The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.

Bit 0: This bit (DTR) controls the DTR output.

Bit 1: This bit (RTS) controls the RTS output.

Bit 2: This bit (OUT1) controls OUT1, a user-designated output signal.

Bit 3: This bit (OUT2) controls OUT2, a user-designated output signal.

When any of bits 0 through 3 are set, the associated output is forced low. When any of these bits are cleared,
the associated output is forced high.

The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.

Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

modem control register (MCR) (continued)

Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP
is set, the following occurs:

The transmitter SOUT is set high.

The receiver SIN is disconnected.

The output of the TSR is looped back into the receiver shift register input.

The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.

The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.

The four modem control outputs are forced to the inactive (high) levels.

Bit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the
detailed description is enabled.

In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify
the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational, but the modem control interrupt's sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.

The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8.

Table 8. ACE Flow Configuration

MCR BIT 5

(AFE)

MCR BIT 1

(RTS)

ACE FLOW CONFIGURATION

Auto-RTS and auto-CTS enabled (autoflow control enabled)

Auto-CTS only enabled

Auto-RTS and auto-CTS disabled

modem status register (MSR)

The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.

Bit 0: This bit is the change in clear-to-send (

CTS) indicator.

CTS indicates that the CTS input has

changed state since the last time it was read by the CPU. When

CTS is set (autoflow control is not enabled

and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control
is enabled (

CTS is cleared), no interrupt is generated.

Bit 1: This bit is the change in data set ready (

DSR) indicator.

DSR indicates that the DSR input has

changed state since the last time it was read by the CPU. When

DSR is set and the modem status interrupt

is enabled, a modem status interrupt is generated.

Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to
the chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled,
a modem status interrupt is generated.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

modem status register (MSR) (continued)

Bit 3: This bit is the change in data carrier detect (

DCD) indicator.

DCD indicates that the DCD input to

the chip has changed state since the last time it was read by the CPU. When

DCD is set and the modem

status interrupt is enabled, a modem status interrupt is generated.

Bit 4: This bit is the complement of the clear-to-send (CTS) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).

Bit 5: This bit is the complement of the data set ready (DSR) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).

Bit 6: This bit is the complement of the ring indicator (RI) input. When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1).

Bit 7: This bit is the complement of the data carrier detect (DCD) input. When the ACE is in the diagnostic
test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).

programmable baud generator

The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz
and divides it by a divisor in the range between 1 and (2

-1). The output frequency of the baud generator is

sixteen times (16

) the baud rate. The formula for the divisor is:

divisor = XIN frequency input

(desired baud rate

16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.

Tables 9 and 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz
respectively. For baud rates of 38.4 kbits/s and below, the error obtained is small. The accuracy of the selected
baud rate is dependent on the selected crystal frequency (see Figure 25 for examples of typical clock circuits).

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

programmable baud generator (continued)

Table 9. Baud Rates Using a 1.8432-MHz Crystal

DESIRED

BAUD RATE

DIVISOR USED
TO GENERATE

CLOCK

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

2304

1536

110

1047

0.026

134.5

857

0.058

150

768

300

384

600

192

1200

1800

2000

0.69

2400

3600

4800

7200

9600

19200

38400

56000

2.86

Table 10. Baud Rates Using a 3.072-MHz Crystal

DESIRED

BAUD RATE

DIVISOR USED
TO GENERATE

CLOCK

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

3840

2560

110

1745

0.026

134.5

1428

0.034

150

1280

300

640

600

320

1200

160

1800

107

0.312

2000

2400

3600

0.628

4800

7200

1.23

9600

19200

38400

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

programmable baud generator (continued)

Driver

Optional

Driver

External

Clock

Optional

Clock

Output

Oscillator Clock
to Baud Generator
Logic

XIN

XOUT

Crystal

XIN

RX2

XOUT

Oscillator Clock
to Baud Generator
Logic

TYPICAL CRYSTAL OSCILLATOR NETWORK

CRYSTAL

RX2

3.072 MHz

1 M

1.5 k

10 - 30 pF

40 - 60 pF

1.8432 MHz

1 M

1.5 k

10 - 30 pF

40 - 60 pF

16 MHz

1 M

33 pF

Figure 25. Typical Clock Circuits

receiver buffer register (RBR)

The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is supplied by the 16

receiver clock (RCLK). Receiver section control is a function of the ACE

line control register.

The ACE RSR receives serial data from SIN. The RSR then concatenates the data and moves it into the RBR
FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt
is enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR.
In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.

scratch register

The scratch register is an 8-bit register that is intended for the programmer's use as a scratchpad in the sense
that it temporarily holds the programmer's data without affecting any other ACE operation.

transmitter holding register (THR)

The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is supplied by BAUDOUT. Transmitter section control is a function of the ACE line control
register.

The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at SOUT. In the TL16C450 mode, if the THR is empty and the
transmitter-holding-register-empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.

TL16C550D, TL16C550DI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS597C - APRIL 2004 - REVISED JUNE 2005

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Revision History

DATE

REV

PAGE

SECTION

DESCRIPTION

RHB Pinout

Change pin 2 to NC and pin 9 to NC

Functional Block Diagram

Change VCC 2,28 to VCC 28 and VSS 9,13 to VSS 9

6/22/05

Change VCC description to 2.25-V to 5.5-V power supply voltage

Change NC to 2, 9, 15, 16

Terminal Functions Table

Change VCC to pin 28 only and VSS to pin 13 only

1, 3

Added RHB package

Added functional block diagram for RHB package

10, 11

Added Terminal Functions table for RHB package

6/02/04

Added Figure 21, Basic TL16C550D Configuration (for RHB Package)

Application Information

Added Figure 24, Typical TL16C550D Connection to a CPU (for RHB
Package)

Mechanical Information

Added RHB Mechanical Data information

4/02/04

Original version

NOTE

Page numbers for previous revisions may differ from page numbers in the current version.

PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

TL16C550DIPFB

ACTIVE

TQFP

PFB

250

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

TL16C550DIPFBR

ACTIVE

TQFP

PFB

1000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

TL16C550DIPT

ACTIVE

LQFP

250

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TL16C550DIPTG4

ACTIVE

LQFP

250

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TL16C550DIPTR

ACTIVE

LQFP

1000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TL16C550DIPTRG4

ACTIVE

LQFP

1000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TL16C550DIRHB

ACTIVE

QFN

RHB

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

TL16C550DPFB

ACTIVE

TQFP

PFB

250

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

TL16C550DPFBR

ACTIVE

TQFP

PFB

1000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

TL16C550DPT

ACTIVE

LQFP

250

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TL16C550DPTG4

ACTIVE

LQFP

250

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TL16C550DPTR

ACTIVE

LQFP

1000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TL16C550DPTRG4

ACTIVE

LQFP

1000

TBD

Call TI

TL16C550DRHB

ACTIVE

QFN

RHB

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco

Plan

The

planned

eco-friendly

classification:

Pb-Free

(RoHS)

Green

(RoHS

Sb/Br)

please

check

http://www.ti.com/productcontent

for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

PACKAGE OPTION ADDENDUM

www.ti.com

22-Jul-2005

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
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such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
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is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products

Applications

Amplifiers

amplifier.ti.com

Audio

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

www.ti.com/broadband

Interface

interface.ti.com

Digital Control

www.ti.com/digitalcontrol

Logic

logic.ti.com

Military

www.ti.com/military

Power Mgmt

power.ti.com

Optical Networking

www.ti.com/opticalnetwork

Microcontrollers

microcontroller.ti.com

Security

www.ti.com/security

Telephony

www.ti.com/telephony

Video & Imaging

www.ti.com/video

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

2005, Texas Instruments Incorporated

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