TL16C754

QUAD UART WITH 64-BYTE FIFO

SLLS279A OCTOBER 1998 REVISED OCTOBER 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

ST16C654 Pin Compatible With Additional
Enhancements

Supports Up To 50-MHz Input Clock
(3 Mbps) for 5-V Operation

Supports Up To 35-MHz Input Clock
(2 Mbps) for 3.3-V Operation

64-Byte Transmit FIFO

64-Byte Receive FIFO With Error Flags

Programmable and Selectable Transmit and
Receive FIFO Trigger Levels for DMA and
Interrupt Generation

Programmable Receive FIFO Trigger Levels
for Software/Hardware Flow Control

Software/Hardware Flow Control
Programmable Xon/Xoff Characters
Programmable Auto-RTS and Auto-CTS

Optional Data Flow Resume by Xon Any
Character

DMA Signalling Capability for Both
Received and Transmitted Data

Supports 3.3-V or 5-V Supply

Characterized for Operation From 40

C to

Software Selectable Baud Rate Generator

Prescalable Provides Additional Divide by 4
Function

Fast Access 2 Clock Cycle IOR/IOW Pulse
Width

Programmable Sleep Mode

Programmable Serial Interface
Characteristics
5, 6, 7, or 8-Bit Characters
Even, Odd, or No Parity Bit Generation

and Detection

 1, 1.5, or 2 Stop Bit Generation

False Start Bit Detection

Complete Status Reporting Capabilities in
Both Normal and Sleep Mode

Line Break Generation and Detection

Internal Test and Loopback Capabilities

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and CD)

22 23

NC
DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
VCC
DTRC
CTSC
DSRC
NC
NC

NC
NC

DSRA

CTSA

DTRA

VCC

RTSA

INTA

CSA

TXA

IOW

TXB

CSB

INTB

RTSB

GND

DTRB

CTSB

DSRB

25 26 27 28

PN PACKAGE

(TOP VIEW)

79 78 77 76 75

RIA

RXA

GND

AL1

RESET

CDB

RIB

RXB

CLKSEL

72 71 70

29 30 31 32 33

69 68

67 66 65 64

34 35 36 37

RXRDY

TXRDY

GND

RXC

INTSEL

RXD

RID

CDA

RIC

CDC

38 39 40

CDD

63 62 61

AL2

NC No internal connection

TL16C754PN

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1999, Texas Instruments Incorporated

TL16C754
QUAD UART WITH 64-BYTE FIFO

SLLS279A OCTOBER 1998 REVISED OCTOBER 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

28 29

DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
VCC
DTRC
CTSC
DSRC

DSRA

CTSA

DTRA

VCC

RTSA

INTA

CSA

TXA

IOW

TXB

CSB

INTB

RTSB

GND

DTRB

CTSB

DSRB

31 32 33 34

8 7

RXA

GND

AL2

RESET

RXRDY

TXRDY

RXB

CLKSEL

AL1

1 68 67

35 36 37 38 39

66 65

CDB

RIB

INTSEL

64 63 62 61

40 41 42 43

GND

RXC

RIC

CDC

VCC

RXD

RID

CDD

CDA

RIA

FN PACKAGE

(TOP VIEW)

TL16C754FN

NC No internal connection

description

The TL16C754 is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic
hardware/software flow control, and data rates up to 3 Mbps. The TL16C754 offers enhanced features. It has
a transmission control register (TCR) that stores received FIFO threshold level to start/stop transmission during
hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY
for all four ports in one access. On-chip status registers provide the user with error indications, operational
status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal
loopback capability allows onboard diagnostics.

The UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on
the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO
and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity
and 1, 1.5, or 2 stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors.
The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control
operations, and software flow control and hardware flow control capabilities.

The TL16C754 is available in 80-pin TQFP and 68-pin PLCC packages.

TL16C754

QUAD UART WITH 64-BYTE FIFO

SLLS279A OCTOBER 1998 REVISED OCTOBER 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

NO.

I/O

DESCRIPTION

NAME

Address bit 0 select. Internal registers address selection. Refer to Table 5 for Register Address Map.

Address bit 1 select. Internal registers address selection. Refer to Table 5 for Register Address Map

Address bit 2 select. Internal registers address selection. Refer to Table 5 for Register Address Map

CDA, CDB
CDC, CDD

79, 23
39, 63

9, 27

43, 61

Carrier detect (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates that a carrier has been detected by the modem for that channel.

CLKSEL

Clock select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable clock. During the reset,
a logic 1 (VCC) on CLKSEL selects the divide-by-1 prescaler. A logic 0 (GND) on CLKSEL selects
the divide-by-4 prescaler. The value of CLKSEL is latched into MCR[7] at the trailing edge of RESET.
A logic 1 (VCC) on CLKSEL will latch a 0 into MCR[7]. A logic 0 (GND) on CLKSEL will latch a 1 into
MCR[7]. MCR[7] can be changed after RESET to alter the prescaler value.

CSA, CSB
CSC, CSD

9, 13,

49, 53

16, 20,

50, 54

Chip select A, B, C, and D (active low). These pins enable data transfers between the user CPU
and the TL16C754 for the channel(s) addressed. Individual UART sections (A, B, C, D) are
addressed by providing a low on the respective CSA through CSD pin.

CTSA, CTSB
CTSC, CTSD

4, 18

44, 58

11, 25

45, 59

Clear to send (active low). These inputs are associated with individual UART channels A through
D. A low on the CTS pins indicates the modem or data set is ready to accept transmit data from the
754. Status can be checked by reading MSR bit 4. These pins only affect the transmit and receive
operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7,
for hardware flow control operation.

D0D2
D3D7

6870,

7175

6668,

I/O

Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information
to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or
receive serial data stream.

DSRA, DSRB
DSRC, DSRD

3, 19

43, 59

10, 26
44, 60

Data set ready (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates the modem or data set is powered on and is ready for data exchange
with the UART.

DTRA, DTRB
DTRC, DTRD

5, 17

45, 57

12, 24
46, 58

Data terminal ready (active low). These outputs are associated with individual UART channels A
through D. A low on these pins indicates that the 754A is powered on and ready. These pins can
be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to
low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a
reset.

GND

16, 36,

56, 76

6, 23,

40, 57

Pwr

Signal and power ground

INTA, INTB
INTC, INTD

8, 14,

48, 54

15, 21,

49, 55

Interrupt A, B, C, and D (active high). These pins provide individual channel interrupts, INTAD.
INTAD are enabled when MCR bit 3 is set to a 1, interrupts are enabled in the interrupt enable
register (IER) and when an interrupt condition exists. Interrupt conditions include: receiver errors,
available receiver buffer data, transmit buffer empty, or when a modem status flag is detected.
INTAD are in the high-impedance state after reset.

INTSEL

Interrupt select (active high with internal pulldown). INTSEL can be used in conjunction with MCR
bit 3 to enable or disable the 3-state interrupts INTAD or override MCR bit 3 and force continuous
interrupts. Interrupt outputs are enabled continuously by making this pin a 1. Driving this pin low
allows MCR bit 3 to control the 3-state interrupt output. In this mode, MCR bit 3 is set to a 1 to enable
the 3-state outputs.

IOR

Read input (active low strobe). A valid low level on IOR will load the contents of an internal register
defined by address bits A0A2 onto the TL16C754 data bus (D0D7) for access by an external
CPU.

IOW

Write input (active low strobe). A valid low level on IOW will transfer the contents of the data bus
(D0D7) from the external CPU to an internal register that is defined by address bits A0A2.

TL16C754
QUAD UART WITH 64-BYTE FIFO

SLLS279A OCTOBER 1998 REVISED OCTOBER 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME

NO.

I/O

DESCRIPTION

NAME

RESET

Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output
and the receiver input will be disabled during reset time. See TL16C754 external reset conditions
for initialization details. RESET is an active high input.

RIA, RIB
RIC, RID

78, 24
38, 64

8, 28

42, 62

Ring indicator (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates the modem has received a ringing signal from the telephone line.
A low to high transition on these input pins generates an modem status interrupt, if it is enabled.

RTSA, RTSB
RTSC, RTSD

7, 15

47, 55

14, 22
48, 56

Request to send (active low). These outputs are associated with individual UART channels A
through D. A low on the RTS pins indicates the transmitter has data ready and waiting to send.
Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is
available. After a reset, these pins are set to 1. These pins only affects the transmit and receive
operation when auto RTS function is enabled through the enhanced feature register (EFR) bit 6,
for hardware flow control operation.

RXA, RXB
RXC, RXD

77, 25
37, 65

7, 29

41, 63

Receive data input. These inputs are associated with individual serial channel data to the 754A.
During the local loopback mode, these RX input pins are disabled and TX data is internally
connected to the UART RX input internally.

RXRDY

Receive ready (active low). RXRDY contains the wire-ORed status of all four receive channel
FIFOs, RXRDY AD. It goes low when the trigger level has been reached or a timeout interrupt
occurs. It goes high when all RX FIFOs are empty and there is an error in RX FIFO.

TXA, TXB
TXC, TXD

10, 12
50, 52

17, 19
51, 53

Transmit data. These outputs are associated with individual serial transmit channel data from the
754A. During the local loopback mode, the TX input pin is disabled and TX data is internally
connected to the UART RX input.

TXRDY

Transmit ready (active low). TXRDY contains the wire-ORed status of all four transmit channel
FIFOs, TXRDY AD. It goes low when there are a trigger level number of spares available. It goes
high when all four TX buffers are full.

VCC

6, 46,

13, 47,

Pwr

Power supply inputs

XTAL1

Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input.
A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see
Figures 10 and 11). Alternatively, an external clock can be connected to XTAL1 to provide custom
data rates.

XTAL2

Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal
oscillator output or buffered clock output.

TL16C754

QUAD UART WITH 64-BYTE FIFO

SLLS279A OCTOBER 1998 REVISED OCTOBER 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

functional block diagram

Control Signals

Modem Control Signals

Divisor

Bus

Interface

Control

and

Status Block

Status Signals

Control Signals

Status Signals

Baud-Rate

Generator

UART_CLK

Receiver Block

Logic

Receiver FIFO

64-Byte

Vote

Logic

Transmitter Block

Logic

Transmitter FIFO

64-Byte

NOTE: The Vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a majority vote to determine

the logic level received. The Vote logic operates on all bits received.

functional description

The TL16C754 UART is pin compatible with the TL16C554 and ST16C654 UARTs. It provides more enhanced
features. All additional features are provided through a special enhanced feature register.

The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or
modems and parallel-to-parallel conversion on data characters transmitted by the processor. The complete
status of each channel of the TL16C754 UART can be read at any time during functional operation by the
processor.

The TL16C754 UART can be placed in an alternate mode (FIFO mode) relieving the processor of excessive
software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can
store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have
selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signalling of DMA
transfers.

The TL16C754 UART has selectable hardware flow control and software flow control. Both schemes
significantly reduce software overhead and increase system efficiency by automatically controlling serial data
flow. Hardware flow control uses the RTS output and CTS input signals. Software flow control uses
programmable Xon/Xoff characters.

The UART will include a programmable baud rate generator that can divide the timing reference clock input by
a divisor between 1 and (2

1). The CLKSEL pin can be used to divide the input clock by 4 or by 1 to generate

the reference clock during the reset. The divide-by-4 clock is selected when CLKSEL pin is a logic 0 or the
divide-by-1 is selected when CLKSEL is a logic 1.

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