Document Outline
- FEATURES
- DESCRIPTION
- block diagram
- absolute maximum ratings over operating free-air temperature range (unl\
ess otherwise noted)
- electrical characteristics over recommended operating free-air temperatu\
re range, VDD = 16 V,
20 C < T A < 70 C, T A =
- supply
- output
- state transitions
- short-circuit protection
- Terminal Functions
- APPLICATION INFORMATION
- overview
- connecting the cell stack
- choosing three or four cells
- undervoltage protection
- charging
- open wire protection
- overvoltage protection and the smart discharge feature
- protection against a runaway charger
- overcurrent protection
- protecting against inductive kick at turn-off
- controlling discharge FET turn-on and turn-off times
- controlling discharge FET turn-on and turn-off times
- TYPICAL CHARACTERISTICS
- IMPORTANT NOTICE
UCC3957 1, UCC3957 2, UCC3957 3, UCC3957 4
SLUS236B JANUARY 1999 REVISED SEPTEMBER 2002
THREE OR FOUR CELL LITHIUM ION
PROTECTOR CIRCUIT
1
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FEATURES
D
Three- or Four-Cell Operation
D
Two-Tier Overcurrent Limiting
D
30-
A Typical Supply-Current Consumption
D
3.5-
A Typical Supply Current in Sleep Mode
D
Smart Discharge Minimizes Losses in
Overcharge Mode
D
6.5-V to 20-V VDD Supply Range
D
Highly Accurate Internal Voltage Reference
D
Externally Adjustable Delays in Overcurrent
Controller
D
Detection of Loss-of-Cell Sense Connections
DESCRIPTION
The UCC3957 is a BiCMOS three- or four-cell
lithium-ion battery pack protector designed to
operate with external P-channel MOSFETs.
Utilizing external P-channel MOSFETs provides
the benefits of no loss-of-system ground in an
overdischarge state, and protects the IC as well as
battery cells from damage during an overcharge
state. An internal state machine runs continuously
to protect each lithium-ion cell from overcharge
and overdischarge. A separate overcurrent-
protection block protects the battery pack from
excessive discharge currents.
If any cell voltage exceeds the overvoltage
threshold, the appropriate external P-channel
MOSFET is turned off, preventing further charge
current. An external N-channel MOSFET is
required to level shift to this high-side P-channel
MOSFET. Discharge current can still flow through
the second P-channel MOSFET. Likewise, if any
cell voltage falls below the undervoltage limit, the
second P-channel MOSFET is turned off and only
charge current is allowed. Such a cell-voltage
condition causes the chip to go into low-power
sleep mode. Attempting to charge the battery
pack wakes up the chip. A cell-count pin (CLCNT)
is provided to program the IC for three- or four-cell
operations.
A two-tiered overcurrent controller and external
current shunt protect the battery pack from
excessive discharge currents. If the first
overcurrent threshold level is exceeded, an
internal timing circuit charges an external
capacitor to provide a user programmable
blanking time. If at the end of the blanking time the
overcurrent condition still exists, the external
discharge FET is turned off for a period 17 times
longer than the first blanking period, and then the
discharge FET is turned back on. If at any time a
second higher overcurrent threshold is exceeded
for more than a user programmable time, the
discharge FET is turned off, and remains off for the
same period as the first tier off time. This two tiered
overcurrent-protection scheme allows for
charging capacitive loads while retaining effective
short-circuit protection.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
CLCNT
WU
AN1
AN2
AN3
AN4
BATLO
DVDD
AVDD
CDLY2
DCHG
CHG
AN4
CDLY1
CHGEN
(TOP VIEW)
M PACKAGE
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
UCC3957 1, UCC3957 2, UCC3957 3, UCC3957 4
SLUS236B JANUARY 1999 REVISED SEPTEMBER 2002
2
www.ti.com
block diagram
UDG00129
1
3
2
CELL
VOLTAGE
SELECT
OVERCURRENT
CONTROLLER
4
6
5
7
8
REFERENCE
VOLTAGE
SELECT AND
COMPARE
REF
STATE
MACHINE
CLOCK
S
Q
R
+
AN4
VDD
BATLO
AN3
AN2
AN1
CLCNT
WU
VDD
UV
SLEEP
16
14
15
13
11
12
10
9
CDLY1
CHGEN
AN4
CHG
AVDD
CDLY2
DVDD
DCHG
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD)
20 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply current
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage:
(WU)
24 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(AN1, AN2, AN3)
VAN4 VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(CLCNT, CHGEN)
15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range (BATLO)
0.3 V to 2.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
55
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature (soldering, 10 seconds)
300
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Unless otherwise indicated, voltages are reference to ground and currents are positive into and negative out of the specified terminals. Consult
Packaging Information section of the Portable Products Databook (TI Literature No. SLUD001) for thermal limitations and considerations of
packages. All voltages are referenced to the AN4 terminal.
AVAILABLE OPTIONS
T
PACKAGED DEVICES
SSOP (M)
TA
NORMAL TO OVERCHARGE VOLTAGE (V)
4.20
4.25
4.30
4.35
20
C to 70
C
UCC3957M1
UCC3957M2
UCC3957M3
UCC3957M4
The M package is available taped and reeled. Add TR suffix to device type (e.g.
UCC3957M1TR) to order quantities of 2500 devices per reel.
UCC3957 1, UCC3957 2, UCC3957 3, UCC3957 4
SLUS236B JANUARY 1999 REVISED SEPTEMBER 2002
3
www.ti.com
electrical characteristics over recommended operating free-air temperature range, VDD = 16 V,
20
_
C < T
A
< 70
_
C, T
A
= T
J
. (unless otherwise noted)
supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDDmin Minimum VDD
5.0
5.5
V
IDD
Supply current
30
40
A
ISL
Sleep-mode supply current
VDD = 10.4 V
3.5
7.5
A
VIN
Input voltage for WU
See Note 2
20
V
output
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
DCHG o tp t c rrent
Driving-logic low,
VO = 1 V
40
70
100
A
IDCHG
DCHG output current
Driving-logic high,
VO = (VDD 1)
13
3
mA
I
CHG ouput current
Driving-logic low,
VO = 1 V
40
70
100
A
ICHG
CHG ouput current
Driving-logic high,
VO = (VDD 1V)
15
3
mA
state transitions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOV
Normal to overcharge voltage
See Note 1
UCC3957 1
4.15
4.20
4.25
V
VOVR
Overcharge to normal voltage
UCC39571
3.95
4.00
4.05
V
VOV
Normal to overcharge voltage
See Note 1
UCC3957 2
4.20
4.25
4.30
V
VOVR
Overcharge to normal voltage
UCC39572
4.00
4.05
4.10
V
VOV
Normal to overcharge voltage
See Note 1
UCC3957 3
4.25
4.30
4.35
V
VOVR
Overcharge to normal voltage
UCC39573
4.05
4.10
4.15
V
VOV
Normal to overcharge voltage
See Note 1
UCC3957 4
4.30
4.35
4.40
V
VOVR
Overcharge to normal voltage
UCC39574
4.10
4.15
4.20
V
VUV
Undercharge to normal voltage
See Note 1
2.5
2.6
2.7
V
VUVR
Normal to undercharge voltage
2.2
2.3
2.4
V
tdOV
Overvoltage to CHG delay
8
17
23
ms
tdUV
Undervoltage to DCHG Delay
8
17
23
ms
tS
Cell sample rate
4
8.5
11.5
ms
VSM
Smart discharge threshold
BATLO voltage
4
15
25
mV
VWU
Wakeup input threshold
With respect to VDD
50
230
750
mV
VCE
Charge-enable input threshold
0.8
1.3
2.6
V
short-circuit protection
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCL1
First-tier threshold level
VBATLO
120
150
190
mV
VCL2
Second-tier threshold level
VBATLO
275
375
450
mV
tB1
First-tier blanking time
CDLY1 = 0.1
F
30
50
70
ms
tRST
Restart time
CDLY1 = 0.1
F
300
500
700
ms
tB2
Second-tier blanking time
CDLY2 = 10 pF
100
400
600
s
NOTE 1: Other overvoltage or undervoltage thresholds are available. Please consult the factory.
2: Refer to Figure 6, for WU leakage characteristics.
UCC3957 1, UCC3957 2, UCC3957 3, UCC3957 4
SLUS236B JANUARY 1999 REVISED SEPTEMBER 2002
4
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AN1
4
I
Connects to the negative terminal of the top battery cell and the positive terminal of the second battery cell.
AN2
5
I
Connects to the bottom terminal of the second battery cell and the top terminal of the third battery cell.
AN3
6
I
Connects to the bottom terminal of the third battery cell and the top terminal of the fourth battery cell in a four
cell stack. In a three cell pack it connects to the bottom terminal of the third battery and to AN4.
AN4
7
I
Connects to the bottom terminal of the battery stack and the top of the current sense resistor.
AVDD
15
O
Internal analog supply bypass cap pin. Connect a 0.1-
F capacitor between this pin and AN4. This pin is
nominally 7.3 V.
BATLO
8
I
Connects to the bottom of the current sense resistor and the negative terminal of the battery pack.
CHGEN
9
I
The charge enable input for the protection IC. This point must be driven high to DVDD or AVDD to allow
charging of the battery pack. This pin has a very weak pulldown.
CDLY1
10
O
Delay control pin for the short-circuit protection feature. A capacitor connected between this point and AN4
determines the time delay from when an overcurrent situation is detected to when the FET is turned off. This
capacitor also controls the hiccup mode timeout period.
CDLY2
14
O
An external cap can be tied between this pin and AN4 to extend the blanking time on the second current limit
tier.
CLCNT
2
I
This pin programs the IC for three or four cell operation. Tying this pin low (to AN4) sets four cell operation,
while tying it high (to DVDD or AVDD) sets three cell operation. This pin is internally pulled low, so open cir-
cuit conditions always result in four-cell mode.
DCHG
13
O
This pin is used to prevent overdischarge. If the state machine indicates that any cell is undervoltage, this pin
is driven high with respect to chip substrate so that the external P-channel MOSFET prevents further dis-
charge. If all cell voltages are above the minimum threshold, this pin is driven low.
CHG
12
O
This pin is used to control an external N-channel MOSFET, which in turn drives a P-channel MOSFET. If at
least one cell voltage is over the overvoltage threshold, this pin is driven low with respect to AN4. If all cell
voltages are below this threshold, this pin is driven high.
DVDD
16
O
Internal digital supply bypass capacitor pin. Connect a 0.1-
F capacitor between this pin and AN4. This pin is
nominally 7.3V.
VDD
1
I
Supply voltage to the IC. Connect this point to the top of the lithium-ion battery stack.
WU
3
I
This pin is used to provide a wakeup signal to the IC during sleep mode. Connect this pin to the drain of the
N-channel level shift MOSFET.
UCC3957 1, UCC3957 2, UCC3957 3, UCC3957 4
SLUS236B JANUARY 1999 REVISED SEPTEMBER 2002
5
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APPLICATION INFORMATION
overview
The UCC3957 provides complete protection against overdischarge, overcharge and overcurrent for a three-
or four-cell lithium-ion battery pack. It uses a flying capacitor technique to sample the voltage across each
battery cell and compare it to a precision reference. If any cell is in overvoltage or undervoltage, the
internal-state machine takes the appropriate action to prevent further charge or discharge. High-side P-channel
MOSFETs are used to independently control charge and discharge current. Figure 1 shows a three-cell
lithium-ion protector application diagram with the optional charge-enable switch. In this application, the diode
D1 protects the MOSFET Q2 from inductive kick at turn-off.
UDG98016
1
3
2
4
DVDD
VDD
CLCNT
WU
AN1
AN2
AN3
AN4
BATLO
CHGEN
AN4
CHG
CDLY2
AVDD
CDLY1
5
7
6
8
16
14
15
13
12
10
11
9
C3
OPTIONAL
+
+
+
PACK ()
Q1
IFR7416
CHARGE
Q3
2N7002
LIION
BATTERY
STACK
S1
CLOSE TO ENABLE CHARGING
Q2
IFR7416
DISCHARGE
R1
1 M
C1
0.1
F
C2
0.1
F
RSENSE
0.025
C5
4.7
F
25 V
DCHG
C4
0.022
F
PACK (+)
D1
1 A, 50 V
Figure 1. Three-Cell Lithium-Ion Protector Application Diagram
UCC3957 1, UCC3957 2, UCC3957 3, UCC3957 4
SLUS236B JANUARY 1999 REVISED SEPTEMBER 2002
6
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APPLICATION INFORMATION
overview (continued)
Figure 2 shows a four-cell protector with optional components to protect the charge FET from excessive
gate-to-source transients. In this application, the Zener diode VR1 and the resistor R2 are optional. They protect
the MOSFET Q1 from excessive open-circuit charger voltage. Diode D1 protects MOSFET Q2 from inductive
kick during turn-off.
UDG98017
1
3
2
4
DVDD
VDD
CLCNT
WU
AN1
AN2
AN3
AN4
BATLO
CHGEN
AN4
CHG
CDLY2
AVDD
CDLY1
5
7
6
8
16
14
15
13
12
10
11
9
C3
OPTIONAL
+
+
+
PACK ()
PACK (+)
Q1
IFR7416
CHARGE
Q2
IFR7416
DISCHARGE
Q3
2N7002
LIION
BATTERY
STACK
+
VR1 18 V
D1
1 A, 50 V
R1 1 M
R2
10 k
C1
0.1
F
C2
0.1
F
C5
4.7
F
25 V
C4
0.022
F
RSENSE
0.025
DCHG
Figure 2. Four-Cell Lithium-Ion Protector Application Diagram
connecting the cell stack
When connecting the cell stack to the circuit, it is important to do so in the proper order. First, the bottom of the
stack should be connected to AN4 . Next, the top of the stack should be connected to VDD. The cell taps can
then be connected to AN1, AN2, and AN3 in any order.
choosing three or four cells
For three-cell packs, the cell-count pin (CLCNT) should be connected to the DVDD pin, and the AN3 pin should
be tied to the AN4 pin. For four-cell applications, the CLCNT pin should be grounded (to AN4) and the AN3 pin
is connected to the positive terminal of the bottom cell in the stack.
UCC3957 1, UCC3957 2, UCC3957 3, UCC3957 4
SLUS236B JANUARY 1999 REVISED SEPTEMBER 2002
7
www.ti.com
APPLICATION INFORMATION
undervoltage protection
When any cell is found to be overdischarged (below the normal-to-undercharge threshold), the state machine
turns off both high-side FETs and enters the sleep mode, where current consumption drops to about 3.5
A.
It remains in sleep mode until the application of a charger is sensed by the wakeup pin (WU) being raised above
VDD.
charging
Once a charger has been applied, the charge FET is turned on as long as the charge-enable input pin (CHGEN)
is pulled up to the DVDD pin. If the CHGEN input is left open (or connected to AN4), the charge FET remains
off.
During charge, the charge and discharge FETs cycle on and off while the device is in the sleep state
(undercharge mode), until the cell voltages are all above the undercharge-to-normal threshold. Once the cell
voltages are above this threshold, the device enters the normal state and the FETs remain on continuously.
While the device is charging and in undercharge mode, there is an approximate on time of 8 ms corresponding
to one sampling period, with a very short off time corresponding to undercharge-voltage detect and sleep-mode;
once WU is pulled back up to PACK(+), wake-up detect again occurs, and a new sampling period/charge cycle
is initiated.
open wire protection
The UCC3957 provides protection against broken-cell sense connections within the pack. If the sense
connection to one of the cells (pins AN1, AN2, or AN3) should become disconnected, weak internal-current
sources make the cells that are connected to that wire appear to be in overcharge and charging of the pack is
prevented.
overvoltage protection and the smart discharge feature
If any cell is charged to a voltage exceeding the normal-to-overcharge threshold, the charge FET is turned off,
preventing further charge current. Hysteresis keeps the charge FET off until the cell voltages have dropped
below the overcharge-to-normal threshold. In most protector designs, the charge FET is held off completely
within this voltage band. During this time, discharge current must be conducted through the body diode of the
charge FET. This forward voltage drop can be as high as 1 V, causing significant power dissipation in the charge
FET and wasting precious battery power.
The UCC3957 has a unique smart discharge feature that allows the charge FET to return to on mode (for
discharge only) while still in the overcharge hysteresis band. This greatly reduces power dissipation in the
charge FET. This is accomplished by sensing the voltage drop across the current-sense resistor. If this drop
exceeds 15 mV (corresponding to 0.6 A of discharge current using a .025
sense resistor), the charge FET
is turned back on. This threshold assures that only discharge current is conducted. In an example using a
20-mW FET with a 1-V body diode drop and a 1-A load, the power dissipation in Q1 would be reduced from 1
W to 0.02 W.
NOTE: A similar technique is not used during charge (when the discharge MOSFET is off due to
cells being in undervoltage) because the charge current should be low while the cells are in
undervoltage.
UCC3957 1, UCC3957 2, UCC3957 3, UCC3957 4
SLUS236B JANUARY 1999 REVISED SEPTEMBER 2002
8
www.ti.com
APPLICATION INFORMATION
protection against a runaway charger
The use of a small N-channel level shifter (Q3 in the application diagrams) allows the IC to interface with the
high-side charge FET (Q1), even in the presence of a runaway charger. Only the drain-source voltage rating
of the charge FET limits the charge voltage that the protection circuit can withstand. The wakeup (WU) pin is
designed to handle input voltages greater than VDD, as long as the current is limited. In the examples shown,
the charge FET's gate-source resistor (R1) provides this current limiting. Note that in Figure 2, a resistor and
zener (R2 and VR1) have been added to protect Q1 against any possibility of a voltage transient exceeding its
maximum gate-source rating.
overcurrent protection
The UCC3957 protects the battery pack from an overload or a hard short circuit using a two-tier overcurrent
protection scheme. The overcurrent protection is designed to go into a hiccup mode when the voltage drop
across an external-sense resistor (connected to the AN4 and BATLO pins) exceeds a certain threshold. In this
mode, the discharge FET is periodically turned off and on until the fault is removed. Once the fault is removed,
normal operation is automatically resumed.
To facilitate charging large capacitive loads, there are two overcurrent threshold voltages, each with its own
user-programmable time delay. This two-tier approach provides fast response to short circuits, while enabling
the battery pack to provide short-duration surge currents. It also facilitates the charging of large filter caps
without causing nuisance overcurrent trips.
The first-tier threshold is 150 mV nominal, corresponding to 6 A using a .025-
sense resistor as shown in the
examples of Figure 1 and Figure 2. If the pack-discharge current exceeds this amount for a period of time,
determined by the capacitor on the CDLY1 pin, it then enters the hiccup mode. The first-tier hiccup duty cycle
is fixed at approximately 6%, minimizing power dissipation in the event of a sustained overload. The absolute
on and off times of the discharge FET (Q2) are controlled by the CDLY1 capacitor. A curve relating the delay
(on time) to this capacitor value is shown in Figure 4. The off time is approximately 17 times longer than the on
time.
The second-tier overcurrent threshold is nominally 375 mV, corresponding to 15 A using a .025-
sense resistor.
If the pack current exceeds this value for a period of time, determined by the capacitor on the CDLY2 pin, it then
enters the hiccup-mode with a much lower duty cycle, typically less than 1%. The relationship of this time delay
(on time) to the CDLY2 capacitor value is shown in the curve of Figure 5. The off time during this hiccup mode
is still determined by the CDLY1 capacitor, as previously described. This technique greatly reduces the stress
and power dissipation in the FETs during short-circuit conditions.
In the examples shown in Figure 1 and Figure 2 (with CDLY1 = .022
F), the first-tier overcurrent on time is
approximately 10 msec, while the off time is approximately 170 msec, resulting in a 5.9% duty cycle for currents
over 6 A (but less than 15 A). If no CDLY2 capacitor is used, the second-tier on time is less than 200
sec
(assuming no stray capacitance), resulting in a duty cycle of about 0.1% for currents over 15 A. If CDLY2 = 22pF,
the typical on time for currents exceeding 15 A is approximately 800
sec, resulting in a duty cycle of 0.5%.
UCC3957 1, UCC3957 2, UCC3957 3, UCC3957 4
SLUS236B JANUARY 1999 REVISED SEPTEMBER 2002
9
www.ti.com
APPLICATION INFORMATION
protecting against inductive kick at turn-off
In the case of a short circuit, the di/dt that occurs when the discharge FET is turned off can result in a significant
voltage undershoot at the pack output due to stray inductance. This undershoot can potentially exceed the
breakdown voltage rating of the discharge FET. A clamp diode (D1 in Figure 1, Figure 2, and Figure 3), or a
capacitor across the pack output, protects against this possibility. A diode also provides protection from a
reverse-polarity charger.
During turn-off, a voltage overshoot can occur at the top of the cell stack, due to wiring inductance and the cells'
internal equivalent series inductance (ESL). During very high di/dt conditions, such as occurs when turning off
in response to a short circuit, this voltage overshoot can be significant and potentially damage the IC or the
discharge FET (Q2). For this reason, it is strongly recommended that a capacitor (C5) be placed across the cell
stack, from VDD to AN4, and that stray inductance be minimized in the battery-current path. Additional methods
to reduce di/dt across the cell stack are discussed in the following section.
controlling discharge FET turn-on and turn-off times
Slew-rate limiting the pack output voltage at turn-on greatly reduces the surge current into large capacitive
loads.
This allows the designer to select shorter overcurrent-delay times, minimizing the stress on Q1 and Q2 in the
event of a shorted pack output. A simple method of implementing slew-rate limiting is shown in Figure 3. It
consists of an RC network (R3 and C6) between gate and drain of the discharge FET (Q2) to control its turn-on
time. This circuit relies on the relatively high-sink impedance (about 20 k
) of the UCC3957's DCHG output.
The values shown for R3 and C6 provide a pack output voltage rise time of about 4.5 ms when the discharge
FET (Q2) is turned on. Note that the addition of R3 and C6 has made it possible to eliminate the CDLY2
capacitor, for the quickest response to a true short circuit. While this circuit does not prevent a large surge current
when inserting a live battery pack into a highly-capacitive load, it does allow it to restart (after one hiccup cycle)
if this initial surge-current trips the overcurrent protection.
Increasing the turn-off time of the discharge FET (Q2) reduces the inductive kick that results during turn-off after
an overcurrent condition. This is accomplished by adding a resistor (R4) in series with the DCHG output. This
reduction of di/dt at turn-off minimizes the need for a capacitor across the battery stack. It is recommended that
this resistor value not exceed a few hundred Ohms, in which case the ability to turn off quickly enough into a
short may be compromised.
Due to the relatively low-charge currents (typically a few Amperes max), controlling the turn-on and turn-off
times of the charge FET is not beneficial. In fact, the turn-off time of the charge FET is slow due to the large value
of R1, the gate-to-source resistor.
UCC3957 1, UCC3957 2, UCC3957 3, UCC3957 4
SLUS236B JANUARY 1999 REVISED SEPTEMBER 2002
10
www.ti.com
APPLICATION INFORMATION
controlling discharge FET turn-on and turn-off times
Figure 3 shows a four-cell protector with slew-rate limiting the discharge FET. In this application, VR1 and R2
are optional, They protect Q1 from excessive open-circuit charger voltage. R3 and C6 are chosen based on
capacitive load that must be driven. R4 minimizes inductive kick at turn-off.
UDG98018
1
3
2
4
DVDD
VDD
CLCNT
WU
AN1
AN2
AN3
AN4
BATLO
CHGEN
AN4
CHG
CDLY2
AVDD
CDLY1
5
7
6
8
16
14
15
13
12
10
11
9
C3
OPTIONAL
+
+
+
PACK ()
PACK (+)
Q1
IFR7416
CHARGE
Q2
IFR7416
DISCHARGE
LIION
BATTERY
STACK
+
VR1 18 V
D1
1 A, 50 V
Q3
2N7002
R2
10 k
C1
0.1
F
C2
0.1
F
C5
4.7
F
25 V
C4
0.022
F
RSENSE
0.025
R1 1 M
R3 1 k
C6
0.22
F
R4
100
DCHG
Figure 3. Four-Cell Lithium-Ion Protector Application Diagram
UCC3957 1, UCC3957 2, UCC3957 3, UCC3957 4
SLUS236B JANUARY 1999 REVISED SEPTEMBER 2002
11
www.ti.com
TYPICAL CHARACTERISTICS
Figure 4
0.001
0.01
0.1
0.1
1
10
100
TYPICAL TIER-ONE OVERCURRENT DELAY TIME
vs
DELAY CAPACITANCE
Off-time
CCDLY1 Delay Capacitance
F
t D
D
e
l
ay
Ti
me
ms
Delay
1000
Figure 5
0
10
20
30
40
0
200
400
600
800
1000
1200
1400
TYPICAL TIER-TWO OVERCURRENT DELAY TIME
vs
DELAY CAPACITANCE
t D
Dela
y
T
ime
s
CCDLY2 Delay Capacitance pF
Figure 6
0
10
50
14
70
16
18
20
22
24
26
20
30
40
60
WU LEAKAGE CURRENT
vs
INPUT VOLTAGE
VWU Wake-Up Input Voltage V
I WU
WU Leakage Current
A
Maximum
Typical
Minimum
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