TLP558
2002-09-25
1
TOSHIBA
Photocoupler
GaAAs IRed & Photo IC
TLP558
Isolated Bus Driver
High Speed Line Receiver
Microprocessor System Interfaces
MOS FET Gate Driver
Transistor Inverter
The TOSHIBA TLP558 consisits of a GaAAs light emitting diode and
integrated high gain, high speed photodetector.
This unit is 8-lead DIP package.
The detector has a three state output stage that provides source drive
and sink drive, and built-in schmitt trigger. The detector IC has an
internal shield that provides a guaranteed common mode transient
immunity of 1000V / s. TLP558 is inverter logic type. For buffer logic
type, TLP555 is in line-up.
l Input current
:
I
F
=1.6mA(max.)
l Power supply voltage: V
CC
=4.5~20V
l Switching speed: t
pHL
, t
pLH
=400ns(max.)
l Common mode transient immunity: 1000V /
s(min.)
l Guaranteed performance over temperature:
-25~85C
l Isolation voltage: 2500V
rms
(min.)
l UL recognized: UL1577, file No. E67349
Truth Table
(positive logic)
Input Enable Output
H H L
L H H
H L Z
L L Z
A 0.1F bypass capacitor must be connected
between pins 8 and 5 (see Note 9).
Pin Configuration
(top view)
1 : NC
2 : Anode
3 : Cathode
4 : NC
5 : GND
6 : V
O
(Output)
7 : V
E
(Enable)
8 : V
CC
1
2
6
8
3
V
CC
GND
Shield
5
4
7
Schematic
Shield
2
3
6
V
CC
V
O
-
+
I
O
V
E
5
7
8
I
E
I
CC
I
F
V
F
GND
Unit in mm
TOSHIBA 11-10C4
Weight: 0.54 g
TLP558
2002-09-25
2
Maximum Ratings
(no derating required up to 85C unless otherwise noted)
Charactersitic Symbol
Rating
Unit
Forward current
I
F
10 mA
Peak transient forward current
(Note 1)
I
FPT
1 A
LE
D
Reverse voltage
V
R
5 V
Output current
I
O
40 /
-25 mA
Peak output current
(Note 2)
I
OP
80 /
-50 mA
Output voltage
V
O
-0.5~20 V
Supply voltage
V
CC
-0.5~20 V
Three state enabel voltage
V
E
-0.5~20 V
Output power dissipation
(Note 3)
P
O
100 mW
Det
e
c
t
or
Total package power dissipation
(Note 4)
P
T
200 mW
Operating temperature range
T
opr
-40~85 C
Storage temperature range
T
stg
-55~125 C
Lead solder temperature(10s)**
T
sol
260 C
Isolation voltage(AC, 1min., R.H. 60%, Ta=25C)
(Note 5)
BV
S
2500 Vrms
(Note 1) Pulse width 1s, 300pps.
(Note 2) Pulse width 5s, duty ratio 0.025.
(Note 3) Derate 1.8mW / C above 70C ambient temperature.
(Note 4) Derate 3.6mW / C above 70C ambient temperature.
(Note 5) Device considered a two terminal device: Pins 1, 2, 3 and 4 shorted together, and pins 5, 6, 7 and 8
shorted together.
**1.6mm below seating plane.
Recommended Operating Conditions
Characteristic Symbol
Min.
Typ.
Max.
Unit
Input current, on
I
F(ON)
2* 5
mA
Input voltage, off
V
F(OFF)
0 0.8 V
Supply voltage
V
CC
4.5 20 V
Enable voltage high
V
EH
2.0 20 V
Enable voltage low
V
EL
0 0.8 V
Fan out(TTL load)
N
4
Operating temperature
T
opr
-25
85 C
*2mA condition permits at least 20% CTR degradation guardband.
Initial switching threshold is 1.6mA or less.
TLP558
2002-09-25
3
Electrical Characteristics
(unless otherwise specified, Ta =
-
-
-
-
25~85C, V
CC
= 4.5~20V)
Characteristic Symbol
Test
Condition
Min.
Typ.*
Max.
Unit
Input forward voltage
V
F
I
F
=5mA, Ta=25C
1.55 1.7 V
Temperature coefficient of
forward voltage
V
F
/ Ta I
F
=5mA
-2.0
mV / C
Input reverse current
I
R
V
R
=5V, Ta=25C
10 A
Input capacitance
C
T
V
F
=0, f=1MHz, Ta=25C
45 pF
V
O
=V
E
=5.5V
100
Output leakage current
(V
O
> V
CC
)
I
OHH
V
F
=0,
V
CC
=4.5V
V
O
=V
E
=20V
0.01 500
A
Logic low output voltage
V
OL
I
OL
=6.4mA, I
F
=1.6mA
V
E
=2V
0.4 0.5 V
Logic high output voltage
V
OH
I
OH
=
-2.6mA, V
F
=0.8V
V
E
=2V
2.4 3.3 V
Logic low enable current
I
EL
V
E
=0.4V
-0.13
-0.32
mA
V
E
=2.7V
20
V
E
=5.5V
100
Logic high enable current
I
EH
V
E
=20V
0.01 250
A
Logic low enable voltage
V
EL
0.8 V
Logic high enable voltage
V
EH
2.0
V
V
CC
=V
E
=5.5V
4.0 6.0
Logic low supply current
I
CCL
I
F
=5mA
V
CC
=V
E
=20V
4.6 7.5
mA
V
CC
=V
E
=5.5V
4.2 6.0
Logic high supply current
I
CCH
V
F
=0V
V
CC
=V
E
=20V
4.7 7.5
mA
I
OZL
V
F
=0V
V
E
=0.8V
V
O
=0.4V
-20
V
O
=2.4V
20
V
O
=5.5V
100
High impedance state
output current
I
OZH
I
F
=5mA
V
E
=0.8V
V
O
=20V
1 500
A
V
O
=V
CC
=5.5V 25 55
Logic low short circuit
output current
(Note 6)
I
OSL
I
F
=5mA
V
E
=2V
V
O
=V
CC
=20V 40 80
mA
V
CC
=5.5V
-10
-25
Logic high short circuit
output current
(Note 6)
I
OSH
V
F
=0V, V
O
=GND
V
E
=2V
V
CC
=20V
-25
-60
mA
Input current logic low
output
I
FL
V
E
=2V, I
O
=6.4mA
V
O
< 0.4V
0.4 1.6 mA
Input voltage logic high
output
V
FH
V
E
=2V, I
O
=
-2.6mA
V
O
> 2.4V
0.8
V
TLP558
2002-09-25
4
Electrical Characteristics
(unless otherwise specified, Ta =
-
-
-
-
25~85C, V
CC
= 4.5~20V)
Characteristic Symbol Test
Condition
Min.
Typ.*
Max.
Unit
Input current hysteresis
I
HYS
V
CC
=V
E
=5V
0.05 mA
Resistance (input
-output) R
S
V
S
=500V, R.H. 60%
Ta=25C (Note
5)
510
10
10
14
Capacitance(input
-output) C
S
V
S
=0, f=1MHz, Ta=25C
(Note
5)
1.0 pF
*All typical values are at Ta=25C, V
CC
=5V, I
F(ON)
=3mA unless otherwise specified.
Switching Characteristics
(unless otherwise specified, V
CC
= 4.5~20V, Ta = 25C)
Characteristic Symbol
Test
Cir
-
cuit
Test Condition
Min.
Typ.*
Max.
Unit
Propagation delay time to
logic high output
(Note 7)
t
pLH
I
F
=3 0mA
250 400 ns
Propagation delay time to
logic low output
(Note 7)
t
pHL
I
F
=0 3mA
270 400 ns
Output rise time (10
-90%) t
r
I
F
=3 0mA, V
CC
=5V
35 75 ns
Output fall time (90
-10%) t
f
1
I
F
=0 3mA, V
CC
=5V
20 75 ns
Output enable time to logic
high
t
pZH
V
E
=0 3V
ns
Output enable time to logic
low
t
pZL
V
E
=0 3V
ns
Output disable time from
logic high
t
pHZ
V
E
=3 0V
ns
Output disable time from
logic low
t
pLZ
2
V
E
=3 0V
ns
Common mode transient
immunity at logic high
output (Note
8)
C
MH
I
F
=0mA, V
CM
=50V
V
O(Min.)
=2V
1000
V
/
s
Common mode transient
immunity at logic low
output (Note
8)
C
ML
3
I
F
=1.6mA, V
CM
=50V
V
O(Max.)
=0.8V
-1000
V
/
s
* All typical values are at Ta=25C, V
CC
=5V
TLP558
2002-09-25
5
(Note 6) Duration of output short circuit time should not exceed 10ms.
(Note 7) The t
pLH
propagation delay is measured from the 50% point on the trailing edge of the input pulse to the
1.3V point on the leading edge of the output pulse. The t
pHL
propagation delay is measured from the 50%
point on the leading edge of the input pulse to the 1.3V point on the trailing edge of the output pulse.
(Note 8) C
ML
is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage
in the logic low state (V
O
> 0.8V).
C
MH
is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage
in the logic state (V
O
> 2.0).
(Note 9) A ceramic capacitor (0.1F) should be connected from pin 8 to pin 5 to stabilize the operation of the high
gain linear amplifier. Failure to provide the bypassing may impair the switching property. The total lead length
between capacitor and coupler should not exceed 1cm.
Test Circuit 1: t
pLH
, t
pHL
, t
r
And t
f
V
OL
1.3V
Input I
F
0mA
V
OH
t
pHL
I
F(ON)
Output V
O
t
r
t
f
90%
10%
50%
t
pLH
V
CC
Pulse generation
t
r
= t
f
= 5ns
V
O
= 5V
D1D4
D2
: 1S1588
C
L
D3
V
CC
GND
Monitor
C
L
is approximately 15pF which includes
probe and stray wiring capacitance.
D1
D4
5V
6
4
3
1
5
7
I
F
Monitor
I
F
V
O
8
2
100
0.1
F
620
5k
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