TLP750
2002-09-25
1
TOSHIBA Photocoupler GaAAs Ired + Photo IC
TLP750
Degital Logic Ground Isolation
Line Receiver
Microprocessor System Interfaces
Switching Power Supply Feedback Control
Analog Signal Isolation
The TOSHIBA TLP750 consists of GaAAs high-output light emitting
diode and a high speed detector of one chip photo diode-transistor.
This unit is 8-lead DIP.
TLP750 has no internal base connection, and is suitable for application in
noisy environmental conditions.
Switching speed: t
pHL
=0.3s(typ.)
Switching speed: t
pLH
=0.5s(typ.)(R
L
=1.9k)
UL recognized: UL1577, file No. E67349
BSI approved: BS EN60065: 1994,
Certificate No.7613
BS EN60950: 1992,
Certificate No.7614
Isolation voltage: 5000V
rms
(min.)
Option(d4)type
VDE approved: DIN VDE0884/06.92,
Certificate No.68384
Maximum operating insulation voltage: 890V
PK
Highest permissible over voltage: 8000V
PK
(Note) When a VDE0884 approved type is needed,
please designate the "Option(D4)"
Creepage distance: 6.4mm(min.)
Clearance: 6.4mm(min.)
Insulation thickness: 0.4mm(min.)
Pin Configuration
(top view)
1
2
8
7
6
5
3
4
1 :
N.C.
2 :
Anode
3 :
Cathode
4 :
N.C.
5 :
Emitter
6 :
Collector
7 :
N.C.
8 :
Cathode
Schematic
2
3
8
6
5
V
F
I
F
V
CC
I
CC
I
O
V
O
GND
TOSHIBA 11
-10C4
Weight: 0.54g
Unit in mm
TLP750
2002-09-25
2
Maximum Ratings
(Ta = 25C)
Characteristic Symbol
Rating
Unit
Forward current
(Note 1)
I
F
25
mA
Pulse forward current
(Note 2)
I
FP
50
mA
Peak transient forward
current
(Note
3)
I
FPT
1
A
Reverse voltage
V
R
5
V
LE
D
Diode power dissipation
(Note
4)
P
D
45
mW
Output current
I
O
8
mA
Peak output current
I
OP
16
mA
Output voltage
V
O
-0.5~15 V
Supply voltage
V
CC
-0.5~15 V
Det
e
c
t
or
Output power dissipation
(Note
5)
P
O
100
mW
Operating temperature range
T
opr
-55~100 C
Storage temperature range
T
stg
-55~125 C
Lead solder temperature(10s)
(Note
6)
T
sol
260
C
Isolation voltage
(AC, 1min., R.H=60%)
(Note
7)
BV
S
5000
V
rms
(Note 1) Derate 0.8mA / C above 70C.
(Note 2) 50% duty cycle, 1ms pulse width.
Derate 1.6mA / C above 70C.
(Note 3) Pulse width 1s, 300pps.
(Note 4) Derate 0.9mW / C above 70C.
(Note 5) Derate 2mW / C above 70C.
(Note 6) Soldering portion of lead: Up to 2mm from the body of the device.
(Note 7) Device considered a two terminal device: Pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted
together.
TLP750
2002-09-25
3
Electrical Characteristics
(Ta = 25C)
Characteristic Symbol
Test
Condition
Min.
Typ.
Max.
Unit
Forward voltage
V
F
I
F
=16mA
1.65 1.85
V
Forward voltage
temperature coefficient
V
F
/ Ta I
F
=16mA
-2
mV / C
Reverse current
I
R
V
R
=5V
10 A
LE
D
Capacitance between
terminal
C
T
V
F
=0, f=1MHz
45 pF
I
OH(1)
I
F
=0mA, V
CC
=V
O
=5.5V
3 500
nA
I
OH(2)
I
F
=0mA, V
CC
=V
O
=15V
5 A
High level output
current
I
OH
I
F
=0mA, V
CC
=V
O
=15V
Ta=70C
50 A
Det
e
c
t
or
High level supply
voltage
I
CCH
I
F
=0mA, V
CC
=15V
0.01 1 A
Ta=25C 10
30
Rank:
0
19
30
Ta=0~70C 5
Current transfer ratio
I
O
/I
F
I
F
=16mA
V
CC
=4.5V
V
O
=0.4V
Rank:
0
15
%
Low level output
voltage
V
OL
I
F
=16mA, V
CC
=4.5V,
I
O
=1.1mA
(rank 0: I
O
=2.4mA)
0.4 V
Isolation resistance
R
S
R.H.=60%, V=5000V
DC
(Note
7)
110
12
10
14
Coupl
ed
Capacitance between
input to output
C
S
V
S
=0, f=1MHz
(Note 8)
0.8 pF
Switching Characteristics
(Ta = 25C, V
CC
= 5V)
Characteristic Symbol
Test
Cir
-
cuit
Test Condition
Min.
Typ.
Max.
Unit
I
F
=016mA, V
CC
=5V,
0.2 0.8
Propagation delay time
(HL)
t
pHL
R
L
=4.1k Rank 0: R
L
=1.9k
0.3 0.8
s
I
F
=160mA, V
CC
=5V,
1.0 2.0
Propagation delay time
(LH)
t
pLH
1
R
L
=4.1k
Rank 0: R
L
=1.9k
0.5 1.2
s
Common mode transient
immunity at logic high
output (Note
8)
C
MH
I
F
=0mA, V
CM
=200V
p
-p
R
L
=4.1k
(Rank 0: R
L
=1.9k)
1500 V
/
s
Common mode transient
immunity at logic low
output (Note
8)
C
ML
2
I
F
=16mA, V
CM
=200V
p
-p
R
L
=4.1k
(Rank 0: R
L
=1.9k)
-1500
V
/
s
TLP750
2002-09-25
4
(Note 8) CML is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage
in the logic low state(V
O
< 0.8V).
CMH is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage
in the logic high state(V
O
> 2.0V).
(Note 9) Maximum electrostatic discharge voltage for any pins: 100V(C=200pF, R=0)
Test Circuit 1: Switching Time Test Circuit
1
8
7
6
5
3
4
2 R
L
V
O
Pulse
Input
PW=100s
Duty ratio=1/10
I
F
Monitor
V
CC
=5V
Output
Monitor
51
1.5V
5V
1.5V
V
O
I
F
0
t
p
HL
t
p
LH
V
OL
I
F
Test Circuit 2: Common Mode Noise Immunity Test Circuit
I
F
V
CC
=5V
R
L
V
O
Pulse generator
V
CM
Z
O
=50
V
CM
V
O
(I
F=0mA)
V
OL
0.8V
2V
5V
0V
200V
90%
10%
t
f
t
r
V
O
(I
F=16mA)
Output
Monitor
1
8
7
6
5
3
4
2
)
(
)
(
=
)
(
)
(
=
s
f
t
V
160
L
CM
,
s
r
t
V
160
H
CM
TLP750
2002-09-25
5
I
OH(1)
Ta
Ambient temperature Ta (C)
H
i
gh l
e
vel
out
put
cu
rr
ent
I OH
(nA
)
300
0.6
100
50
30
10
5
3
1
0 40 80
120
160
V
F
/Ta I
F
Forward current IF (mA)
Fo
rw
ar
d v
o
l
t
age
te
mp
er
atu
r
e
coef
fi
ci
en
t
V
F
/
Ta
(
m
V
/
C
)
-2.6
-1.4
0.1
-2.4
-2.2
-2.0
-1.8
-1.6
0.3 0.5
1
3 5
10
30
I
F
V
F
Forward voltage VF (V)
Fo
rw
ar
d
c
u
r
r
en
t I
F
(mA
)
1.0 1.2 1.4 1.6 1.8 2.0
100
0.01
30
10
3
1
0.3
0.1
0.03
Ta = 25
I
O
I
F
Outp
ut
cur
r
e
n
t I
O
(mA
)
Forward current IF (mA)
0.01
0.1
10
5
3
1
0.5
0.1
0.05
0.3
0.03
0.3 1 3 10 30 100
300
VCC = 5 V
VO = 0.4 V
Ta = 25
I
O
/I
F
I
F
C
u
rr
ent
tr
ans
fer
r
a
ti
o
I O
/I
F
(%
)
Forward current IF (mA)
1
0.3
100
50
30
10
5
3
0.5 1
3 5 10
30
50
VCC = 5 V
VO = 0.4 V
Ta = -25
25
100
Ambient temperature Ta (C)
I
O
/I
F
Ta
No
r
m
a
liz
e
d
I O
/I
F
-40
1.2
0
1.0
0.8
0.6
0.4
0.2
-20 0 20 40 60 80 100
Normalized to:
IF = 16mA
VCC = 4.5V
VO = 0.4V
Ta = 25C
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