VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
High Performance 16x16
Serial Crosspoint Switch
G52191-0, Rev 4.2
Page 1
01/05/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Features
VSC880 Block Diagram
16x16 Synchronous Serial Crosspoint Switch
Serial Data Rates: 2.0Gb/s
32Gb/s Aggregate Data Bandwidth
Parallel Switches Can Increase Data Bandwidth in
Multiples of 32Gb/s
Designed in Conjunction with the VSC870
Backplane Transceiver
Automatic Word and Cell Synchronization to the
Transceiver
Two Modes of Operation: Distributed Control
Self-routing Packet Mode and Central Control
Cell Mode
Multicast Supported in All Modes
Supports Variable Length Packets in Packet
Mode
Built-in Flow Control Channel in Packet Mode
Supports Cell Synchronization in Cell Mode
Parallel CPU Interface and Parallel Switch
Configuration Interface
Loopback, Built-in Self Test and Scan Functions
5V Tolerant TTL Inputs
Dual 3.3V/2.5V or Dual 3.3V/2.0V Power
Supplies
Serial Port Quadrants Can be Powered Down
Available in 304 BGA Package
Serial
to
Parallel
Parallel
to
Serial
DRU
Port
Logic
Serial Port (16x)
Arbitration Logic
and Switch Control
CMU
Clock
Gen
Switch Matrix
TXS+/TXS-
RXS+/RXS-
WCLK
CCLK
CMODE
RESET
TESTEN
SCANIN
SCANOUT
INT
CDATA[7:0]
ADDR[5:0]
CWEN
CEN
TCLKEN
RESYNEN
BSTEN
BSTRST
BSTPASS
DATA[15:0]
CSEL
REFCLK
MEN
FI[3:0]
WEN
Status and
Control Registers
BIST Logic
BSTLPBK
FACLPBK
Registers
LOCKDET
VSCOPNC
VSCTE
VSCIPNC
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
High Performance 16x16
Serial Crosspoint Switch
Page 2
G52191-0, Rev 4.2
01/05/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
General Description
The VSC880 is a 16x16 serial crosspoint switch with serial data rates at 2.125Gb/s. The VSC880 has been
designed to operate with the VSC870 backplane transceiver to establish a synchronous high performance switching
system with an aggregate bandwidth of 32Gb/s. The switch chip transmits the master word clock (62.5Mb/s), and
master cell clock (if used) to all port cards through the serial data channels. The transceivers automatically perform
bit alignment, word alignment and cell alignment to the switch chip. The transceiver and switch chip have been
optimized for both self-routing and cell-based systems and include special commands for connection requests (self-
routing) and cell synchronous operation (cell based). In addition, a parallel CPU interface can be used to control
internal modes and read status information from the switch. A 20-bit interface can also be used to program the switch
matrix in 4 clock cycles. The switch chip runs off of a 3.3V/2.5V or 3.3V/2.0V power supplies. The serial I/O buffers
contain on-chip termination resistors (see Application Note 34).
Pin Descriptions
Pin
Name
I/O
Freq
Type
Description
TXS[15:0]+/
TXS[15:0]-
Transmit Serial Outputs
O
2.125Gb/s
LVDS
16 high speed serial differential transmit channels
RXS[15:0]+/
RXS[15:0]-
Receive Serial Inputs
I
2.125Gb/s
LVDS
16 high speed serial differential receive channels
DATA[15:0]
Configuration Data Input
I
62.5Mb/s
TTL
Parallel input signals used to program the switch matrix in 4
clock cycles when the signal CEN is LOW.
FI[3:0]
Force IDLE Input
I
62.5Mb/s
TTL
Parallel input signals used to program force IDLE words at
the switch matrix output in 4 clock cycles when the signal
CEN is LOW.
CEN
Configure Enable
I
62.5Mb/s
TTL
When CEN is held LOW, the inputs DATA[15:0] and FI[3:0]
can be used to program the switch matrix in 4 word clock
cycles timed to the WEN signal.
WEN
Write Enable
I
62.5Mb/s
TTL
If CEN is LOW, this signal provides a synchronization pulse
for loading switch configuration data into DATA[15:0] and
FI[3:0].
ADDR[5:0]
Data Address
I
62.5Mb/s
TTL
The address to read and write data through parallel interface
CDATA[7:0].
CSEL
Chip Select
I
62.5Mb/s
TTL
This signal allows several switch chips to share an 8 bit data
bus connected to CDATA[7:0]. If CSEL is LOW, data will
be read or written to CDATA[7:0]. If CSEL is HIGH, the
outputs will be high impedance and the inputs disabled.
CDATA[7:0]
Status Data Output
B
62.5Mb/s
TTL
Bidirectional CPU interface for the status and control
registers. If CSEL is LOW, the data will be read or written
into this port. If CSEL is HIGH, the outputs will be high
impedance and the inputs will be disabled.
CWEN
Control Write Enable
I
62.5Mb/s
TTL
This signal is set HIGH to read the internal status registers
through the parallel interface CDATA[7:0]. It is set LOW to
write into this interface.
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
High Performance 16x16
Serial Crosspoint Switch
G52191-0, Rev 4.2
Page 3
01/05/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
RESYNEN
Resynch Enable
I
<1MHz
TTL
If RESYNEN is HIGH, all links that have a link error
condition will be reinitialized. This will override the internal
control register settings.
INT
Interrupt
O
<1MHz
TTL
If INT is LOW, a receive error has occurred in one of the
links that has it's output enable (OE) bit set HIGH and
interrupt control register bit set HIGH.
MEN
Reserved
I
<1MHz
TTL
This signal is reserved for future use and should be set LOW
during normal operation.
FACLPBK
Facility Loop Back
I
<1MHz
TTL
If this signal is set HIGH, all serial inputs are looped back to
their serial outputs. This will override the internal control
register setting.
CMODE
Cell Mode
I
<1MHz
TTL
CMODE is set HIGH for Cell Mode operation.
TESTEN
Scan Test Enable
I
<1MHz
TTL
This signal is used in ATE testing to measure propagation
delay. It is also used in ATE testing of the BIST logic. Set to
logic LOW in normal operation.
SCANIN
Scan Data In
I
62.5Mb/s
TTL
The input signal for measuring propagation delay on the
ATE tester.
SCANOUT
Scan Data Out
O
62.5Mb/s
TTL
The output signal for measuring propagation delay on the
ATE tester. When TESTEN is set LOW, the longer delay
path is enabled.
WCLK
Word Clock
O
62.5MHz
TTL
This is the word clock output.
REFCLK
Reference Clock
I
62.5MHz
TTL
This is the reference clock and the source of the system wide
word clock period.
TCLKEN
Test Clock Enable
I
<1MHz
TTL
This input is set HIGH in test mode, so that the CMU is
bypassed and the REFCLK becomes the bit clock. This
signal is for ATE test only. Set LOW in normal operation.
CCLK
Cell Clock
I
62.5MHz
TTL
This is the source of the system wide cell clock. It is
internally synchronized to the REFCLK. In Packet mode, set
this signal HIGH to enable external switch configuration for
BIST.
RESET
Reset
I
<1MHz
TTL
Global chip reset (active LOW)
BSTLPBK
Built-in Self Test Loop
Back
I
<1MHz
TTL
When BSTLPBK is set HIGH and TESTEN is LOW, all
serial data output signals are looped back to their serial data
inputs. If BSTLPBK is set HIGH and TESTEN is HIGH,
only ports 0-7 are placed in loopback.
BSTEN
Built-in Self Test Enable
I
<1MHz
TTL
When BSTEN is HIGH, at-speed built-in self testing is
enabled.
BSTRST
Built-in Self Test Reset
I
<1MHz
TTL
The BSTRST signal is set HIGH to reset the PRBS
generator and comparator.
BSTPASS
Built-in Self Test Pass
O
<1MHz
TTL
The BSTPASS signal is HIGH if BTSEN is HIGH and the
PRBS comparator detects the correct pattern in built-in self
test mode.
Pin
Name
I/O
Freq
Type
Description
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
High Performance 16x16
Serial Crosspoint Switch
Page 4
G52191-0, Rev 4.2
01/05/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Functional Description
The VSC880 switch can be used in conjunction with the VSC870 transceivers to support two modes of
operation: Packet Mode and Cell Mode. In Packet mode, the chip set provides a switching system to support variable
length, self-routing data packets. In Cell Mode, the chip set provides a cell synchronous switching system with a user
defined scheduler. In this mode, it can support only fixed length data packets (cells). Routing decisions are carried
out in the scheduler and crosspoint configuration is synchronized to a cell clock. The scheduler configures the switch
matrix using the parallel interface. To conserve power, each serial port quadrant can be powered down if not used.
The following section gives a detailed functional description of the operation of the switch chip. Most of the
discussion includes some of the transceiver operation (see the VSC870 data sheet). The two major operation modes
are described separately in the Packet Mode and the Cell Mode sections.
1.0 Common Features
1.1 Synchronization
1.1.1 Link Characteristic
The serial link is used to connect the switch chip to transceivers. These links operate at 2.125 Gb/s and are
initialized simultaneously at power up, or separately when a link error occurs. A link is first bit synchronized, then
word synchronized and, if CMODE is HIGH, cell synchronized. In Packet or Cell mode, the switch acts as the
master, generating the bit clock along with the word and cell boundary information. The transceivers act as slaves,
recovering the bit clock, word clock and cell clock. The transceiver also contains redundant serial inputs and outputs
which can be used with a redundant switch chip.
LOCKDET
CMU Lock Detect
O
<1MHz
TTL
This signal is LOW while the CMU is acquiring lock.
VSCTE
NOR Chain Test Enable
I
<1MHz
TTL
Used for ATE testing of the parametric NOR chain in the I/O
frame. Set to logic LOW during normal operation.
VSCIPNC
NOR Chain Input
I
<1MHz
TTL
Used for ATE testing of the parametric NOR chain in the I/O
frame. Set to logic LOW during normal operation.
VSCOPNC
NOR Chain Output
O
<1MHz
VECL
Used for ATE testing of the parametric NOR chain in the I/O
frame. Leave output open during normal operation.
VDD1, VDD2,
VDD3, VDD4
Serial Port Power
Supplies
P
3.3V
VDD1 = Serial Port 0-3 power supply
VDD2 = Serial Port 4-7 power supply
VDD3 = Serial Port 8-11 power supply
VDD4 = Serial Port 12-15 power supply
VDDA
CMU Power Supply
P
3.3V
Clean power supply for CMU
VSSA
CMU Ground
P
0V
Clean ground for CMU
VMM
Core Power Supply
P
2 ~ 2.5V
Core power supply
Pin
Name
I/O
Freq
Type
Description
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
High Performance 16x16
Serial Crosspoint Switch
G52191-0, Rev 4.2
Page 5
01/05/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
1.1.2 Data Scrambling
To allow the VSC870 CRU to recover the bit clock, a 15% edge transition density must be guaranteed on the
serial data links. All command words and connection request words contain this required density. In order to get this
density on data words, scrambling must be employed by the transceiver (see VSC870 data sheet).
1.1.3 Bit Synchronization
In Packet Mode and Cell Mode, the switch acts as the source of the bit clock. It multiplies the local 62.5MHz
reference clock by 34 to generate a 2.125GHz clock and uses this clock to serialize the 32-bit word and 2 overhead
bits. The transceiver receives and feeds this serial data stream to a digital CRU to recover the bit clock and
deserialize the data stream to a 32-bit word plus 2 overhead bits at 62.5MHz. The transceiver also uses this recovered
clock to serialize its transmit words that are sent to the switch. In this way, the switch and all the transceivers are
frequency-locked to one clock source which is provided by the reference clock on the switch card. Because of this,
the switch chip needs to recover only the phase information on the serial receive channel using a data recovery unit
(DRU). The DRU is designed as a delay lock loop and remains phase-locked to the incoming data stream as long as
the temperature does not change by more than 20C after link initialization. If this temperature variation is exceeded,
a link error may occur causing the link to reinitialize. Because of this, system reset should be held until the system
reaches temperature stability before starting the link initializing process.
1.1.4 Word Synchronization
During power up or at reset, the transceiver can initiate the word synchronization process. First, the transceiver
sends reset patterns to the switch to request that the switch starts the initialization process. The switch, upon
receiving this request, will send out special ALIGN words. The transceiver receives this serial data stream and word
aligns to this ALIGN word by adjusting its own word boundary one bit at a time. Upon detecting the correct word
alignment, it starts the transmit word alignment process. In this process, the transceiver continuously sends ALIGN
words to the switch. The switch uses its own word clock (REFCLK) to detect this ALIGN word. If the transmitters
word is not aligned to the switch chip word clock when it arrives at the switch, the switch chip continues to send out
ALIGN words. After receiving 32 ALIGN words from the switch chip, the transceiver changes its transmit word
boundary by 1 bit position and repeats the process (this limits the distance from the transceiver to the switch to less
than 180ns one way). If the switch detects the transceivers ALIGN word correctly, it sends IDLE words to the
transceiver to signal that the transmitter has now word synchronized with the switch. It also clears the internal
registers LERR, TERR, DERR and CERR and sets the signal INT HIGH if all the enabled serial channels are
successfully initialized (see section 1.4).
1.1.5 Cell Synchronization
If CMODE is set HIGH, after the word synchronization process completes, the transceiver starts the cell
synchronization process. In this process, the transceiver detects the received cell clock (CCLK) sent from the switch
embedded in the alignment word. The switch delays the global cell clock to adjust out the pipeline delay from the
transceiver to the switch. The switch chip does this by connecting each port to itself during link initialization. By
sending an ALIGN words to itself, the transceiver can adjust the transmit clock until it is properly phase shifted
relative to the global cell clock. If cells are sent from the transceiver aligned to this transmit cell clock, they will
arrive at the switch aligned to the master cell clock which is originated at the switch. For this alignment process to
work, the minimum cell size is 8 words (32 bytes).
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