1
White Microelectronics Phoenix, AZ (602) 437-1520
WC32P040-XXM
68040 FEATURES
s Selection of Processor Speeds: 25, 33MHz
s Military Temperature Range: - 55
C to +125
C
s Packaging
179 pin Ceramic PGA (P4)
184 lead Ceramic Quad Flatpack, CQFP (Q4)
s 6-Stage Pipeline, 68030-Compatible IU
s 68881/68882-Compatible FPU
s Independent Instruction and Data MMUs
s Simultaneously Accessible, 4-Kbyte Physical Instruction
Cache and 4-Kbyte Physical Data Cache
s Low-Latency Bus Acceses for Reduced Cache Miss Penalty
s Multimaster/Multiprocessor Support via Bus Snooping
s Concurrent IU, FPU, MMU, and Bus Controller Operation
Maximizes Throughput
s 32-Bit, Nonmultiplexed External Address and Data Buses
with Synchronous Interface
July 1998
FIG. 1
BLOCK DIAGRAM
s User Object-Code Compatible with all Earlier 68000
Microprocessors
s 4-GigaByte Direct Addressing Range
DESCRIPTION
The WC32P040 is a 68000-compatible, high-performance, 32-
bit microprocessor. The WC32P040 is a virtual memory
microprocessor employing multiple concurrent execution units
and a highly intergrated architecture that provides very high
performance in a monolithic HCMOS device. It has a 68030-
compatible integer unit (IU) and two independent caches. The
WC32P040 contains dual, independent, demand-paged memory
management units (MMUs) for instruction and data stream
accesses and independent, 4-Kbyte instruction and data
caches. The WC32P040 has a 68881/68882-compatible
floating-point unit (FPU).
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White Microelectronics Phoenix, AZ (602) 437-1520
FIG. 2
PIN CONFIGURATION FOR WC32P040-XXM, CQFP (Q4)
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
GND
GND
A
31
A
30
V
CC
A
29
A
28
GND
A
27
A
26
V
CC
A
25
A
24
GND
A
23
A
22
V
CC
A
21
A
20
GND
A
19
A
18
V
CC
GND
A
17
A
16
GND
A
15
A
14
V
CC
A
13
A
12
GND
A
11
A
10
GND
V
CC
TT
1
TT
0
GND
UPA
1
UPA
0
V
CC
CIOUT
IPEND
GND
RSTO
TD
0
TD
1
TCK
GND
TRST
TMS
GND
V
CC
MDIS
CDIS
RSTI
IPL
2
IPL
1
IPL
0
GND
GND
BCLK
V
CC
GND
V
CC
GND
PCLK
GND
GND
DLE
GND
GND
TCI
AVEC
TBI
V
CC
GND
SC
0
SC
1
BG
TEA
TA
PST
0
GND
PST
1
PST
2
V
CC
PST
3
TIP
GND
D
27
GND
D
28
D
29
V
CC
D
30
D
31
GND
GND
A
9
A
8
V
CC
A
7
A
6
GND
A
5
A
4
V
CC
A
3
A
2
GND
A
1
A
0
V
CC
GND
TM
2
TM
1
GND
TM
0
TLN
1
V
CC
TLN
0
SIZ
0
GND
R/W
LOCKE
V
CC
GND
SIZ
1
LOCK
GND
MI
BR
V
CC
TS
BB
D
0
D
1
V
CC
GND
D
2
D
3
GND
D
4
GND
D
5
V
CC
D
6
D
7
GND
D
8
D
9
V
CC
GND
D
10
D
11
GND
D
12
D
13
V
CC
D
14
D
15
GND
D
16
D
17
V
CC
GND
D
18
D
19
GND
D
20
D
21
V
CC
D
22
V
CC
D
23
GND
D
24
D
25
GND
V
CC
D
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
WC32P040-XXM
TOP VIEW
Pin Group
GND
Vcc
PLL
17,22,24
19,21
Internal Logic
5,8,10,27,28,33,55,68,95,108,121,
9,32,56,69,81,94,100,109,122,136,149,
130,135,162,174
161,175
Output Drivers 16,20,25,40,46,52,59,65,72,78,84,85, 43,49,62,75,88,102,115,128,143,155,
91,98,105,112,118,125,132,139,140,
168,181
146,152,158,165,171,178,184
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White Microelectronics Phoenix, AZ (602) 437-1520
WC32P040-XXM
FIG. 3
PIN CONFIGURATION FOR WC32P040-XXM, PGA (P4)
IPEND
CIOUT
UPA
1
A
10
A
12
A
13
A
14
A
15
A
17
A
18
A
20
A
21
A
22
A
24
A
27
A
29
A
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
TDO
GND
V
CC
GND
TT1
GND
V
CC
GND
A
16
A
19
GND
V
CC
GND
A
26
GND
V
CC
GND
D
3
TRST
TDI
RTSO
UPA
0
TT
0
A
11
V
CC
GND
GND
V
CC
V
CC
A
23
A
25
A
28
A
30
D
0
D
1
D
4
GND
TCK
GND
D
2
GND
D
5
CDIS
TMS
V
CC
V
CC
V
CC
D
6
IPL
2
MDIS
GND
GND
GND
D
7
IPL
1
RSTI
BCLK
GND
D
8
D
9
IPL
0
V
CC
V
CC
V
CC
GND
D
10
DLE
GND
PCLK
GND
V
CC
D
11
TCI
GND
GND
V
CC
GND
D
12
AVEC
TBI
GND
GND
D
16
D
13
BB
GND
V
CC
GND
SIZ
0
GND
V
CC
GND
TM
2
A
2
GND
V
CC
GND
D
30
GND
V
CC
GND
D
21
BR
LOCK
LOCKE
TLN
0
TLN
1
TM
0
TM
1
A
0
A
1
A
3
A
4
A
5
A
7
A
8
D
31
D
28
D
26
D
24
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
V
CC
D
18
D
14
GND
GND
D
15
V
CC
V
CC
D
17
D
23
GND
D
19
PST
3
V
CC
TS
MI
SIZ
1
R/W
GND
V
CC
GND
V
CC
V
CC
A
6
A
9
D
29
D
27
D
25
D
22
D
20
SC
0
SC
1
V
CC
BG
TEA
GND
TA
PST
1
PST
2
PST
0
GND
TIP
BOTTOM VIEW
Pin Group
GND
Vcc
PLL
S9,R6,R10
R8,S8
Internal Logic
C6,C7,C9,C11,C13,K3,L3,M16,R4,
C5,C8,C10,C12,C14,H3,H16,J3,J16,
R11,R13,S6,S10,T4
L16,M3,R5,R12
Output Drivers B2,B4,B6,B8,B10,B13,B15,B17,D2,
B5,B9,B14,C2,C17,G2,G17,M2,M17,
D17,F2,F17,H2,H17,L2,L17,N2,N17,
R2,R17,S16
Q2,Q17,S2,S15,S17
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White Microelectronics Phoenix, AZ (602) 437-1520
WC32P040-XXM
ADDRESSING MODES
Addressing
Syntax
Register Direct
Data Register Direct
Dn
Address Register Direct
An
Register Indirect
Address Register Indirect
(An)
Address Register Indirect with Postincrement
(An) +
Address Register Indirect with Predecrement
- (An)
Address Register Indirect with Displacement
(d
16
,An)
Register Indirect with Index
Address Register Indirect with Index (8-Bit Displacement)
(d
8
,An,Xn)
Address Register Indirect with Index (Base Displacement)
(bd,An,Xn)
Memory Indirect
Memory Indirect Postindexed
([bd,An],Xn,od)
Memory Indirect Preindexed
([bd,An,Xn],od)
Program Counter Indirect with Displacement
(d
16
,PC)
Program Counter Indirect with Index
PC Indirect with Index (8-Bit Displacement)
(d
8
,PC,Xn)
PC Indirect with Index (Base Displacement)
(bd,PC,Xn)
Program Counter Memory Indirect
PC Memory Indirect Postindexed
([bd,PC],Xn,od)
PC Memory Indirect Preindexed
([bd,PC,Xn],od)
Absolute
Absolute Short
(xxx).W
Absolute Long
(xxx).L
Immediate
#<xxx>
Operand Data Format
Size
Supported In
Notes
Bit
1 Bit
IU
Bit Field
1-32 Bits
IU
Field of Consecutive Bits
Binary-Coded Decimal (BCD)
8 Bits
IU
Packed: 2 Digits/Byte;
Unpacked: 1 Digit/Byte
Byte Integer
8 Bits
IU, FPU
Word Integer
16 Bits
IU, FPU
Long-Word Integer
32 Bits
IU, FPU
Quad-Word Integer
64 Bits
IU
Any Two Data Registers
16-Byte
128 Bits
IU
Memory Only, Aligned to
16-Byte Boundary
Single-Precision Real
32 Bits
FPU
1-Bit Sign, 8-Bit Exponent,
23-Bit Fraction
Double-Precision Real
64 Bits
FPU
1-Bit Sign,11-Bit Exponent,
52-Bit Fraction
Extended-Precision Real
80 Bits
FPU
1-Bit Sign,15-Bit Exponent,
64-Bit Mantissa
ADDRESSSING
The WC32P040 supports the basic addressing modes of the
68000 family. The register indirect addressing modes support
postincrement, predecrement, offset, and indexing. The
program counter indirect mode also has indexing and offset
capabilities.
DATA FORMATS
Opcode
Operation
Syntax
ABCD
BCD Source + BCD Destination + X Destination
ABCD Dy,Dx
ABCD -(Ay),-(Ax)
ADD
Source + Destination Destination
ADD <ea>,Dn
ADD Dn,<ea>
ADDA
Source + Destination Destination
ADDA <ea>,An
ADDI
Immediate Data + Destination Destination
ADDI #<data>,<ea>
ADDQ
Immediate Data + Destination Destination
ADDQ #<data>,<ea>
ADDX
Source + Destination + X Destination
ADDX Dy,Dx
ADDX -(Ay),-(Ax)
AND
Source
Destination Destination
AND <ea>,Dn
AND Dn,<ea>
ANDI
Immediate Data
Destination Destination
ANDI #<data>,<ea>
ANDI to CCR
Source
CCR CCR
ANDI #<data>,CCR
ANDI to SR
If supervisor state
ANDI #<data>,SR
then Source
SR SR
else TRAP
ASL,ASR
Destination Shifted by count Destination
ASd Dx,Dy
(1)
ASd #<data>,Dy
(1)
ASd <ea>
(1)
Bcc
It condition true
Bcc <label>
then PC + dn PC
INSTRUCTION SET SUMMARY
DATA FORMATS
The WC32P040 supports the basic data formats of the 68000
family. Some data formats apply only to the IU, some only to
the FPU, and some to both. In addition, the instruction set
supports operations on other data formats such as memory
addresses.
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White Microelectronics Phoenix, AZ (602) 437-1520
WC32P040-XXM
INSTRUCTION SET SUMMARY (cont.)
Opcode
Operation
Syntax
BCHG
~(bit number of Destination) Z;
BCHG Dn,<ea>
~(bit number ot Destination) (bit number) of Destination
BCHG #<data>,<ea>
BCLR
~(bit number ot Destination) Z;
BCLR Dn,<ea>
0 bit number ot Destination
BCLR #<data>,<ea>
BFCHG
~(bit field ot Destination) bit field of Destination
BFCHG <ea> {offset:width}
BFCLR
0 bit field of Destination
BFCLR <ea> {offset:width}
BFEXTS
bit field of Source Dn
BFEXTS <ea> {offset:width}, Dn
BFEXTU
bit offset of Source Dn
BFEXTU <ea> {offset:width}, Dn
BFFFO
bit offset of Source Bit Scan Dn
BFFFO <ea> {offset:width}, Dn
BFINS
Dn bit field of Destination
BFINS Dn,<ea> {offset:width}
BFSET
1s bit field of Destination
BFSET <ea> {offset:width}
BFTST
bit field of Destination
BFTST <ea> {offset:width}
BKPT
Run breakpoint acknowledge cycle; TRAP as illegal instruction
BKPT #<data>
BRA
PC+d
n
PC
BRA <label>
BSET
~(bit number ot Destination) Z;
BSET Dn,<ea>
1 bit number of Destination
BSET #<data>,<ea>
BSR
SP - 4 SP; PC (SP); PC + dn PC
BSR <label>
BTST
(bit number of Destination) Z
BTST Dn,<ea>
BTST #<data>,<ea>
CAS
CAS Destination Compare Operand cc;
CAS Dc,Du,<ea>
if Z, Update Operand Destination
else Destination Compare Operand
CAS2
CAS2 Destination 1 Compare 1 cc;
CAS2 Dc1-Dc2,Du1-Du2,(Rn1)-(Rn2)
if Z, Destination 2 Compare cc;
if Z, Update 1 Destination 1;
Update 2 Destination 2
else Destination 1 Compare 1;
Destination 2 Compare 2
CHK
If Dn < 0 or Dn > Source then TRAP
CHK <ea>,Dn
CHK2
If Rn < LB or If Rn > UB then TRAP
CHK2 <ea>,Rn
CINV
If supervisor state
CINVL <caches>,
then invalidate selected cache lines
(An) CINVP <caches>,
else TRAP
(An) CINVA <caches>
CLR
0 Destination
CLR <ea>
CMP
Destination Source cc
CMP <ea>,Dn
CMPA
Destination Source
CMPA <ea>,An
CMPI
Destination Immediate Data
CMPI #<data>,<ea>
CMPM
Destination Source cc
CMPM (Ay)+,(Ax)+
CMP2
Compare Rn < LB or Rn > UB and Set Condition Codes
CMP2 <ea>,Rn
CPUSH
If supervisor state
CPUSHL <caches>, (An)
then it data cache push selected dirty data cache lines;
CPUSHP <caches>, (An)
invalidate selected cache lines
CPUSHA <caches>
else TRAP
DBcc
If condition false
DBcc Dn,<label>
then (Dn-1 Dn;
if (Dn
-1
then PC + dn PC)
DIVS, DIVSL
Destination + Source Destination
DIVS.W <ea>,Dn
32 + 16 16r:16q
DIVS.L <ea>,Dq
32 + 32 32q
DIVS.L <ea>,Dr:Dq
64 + 32 32r:32q
DIVSL.L <ea>,Dr:Dq
32 + 32 32r:32q
DIVU, DIVUL
Destination + Source Destination
DIVU.W <ea>,Dn
32 + 16 16r:16q
DIVU.L <ea>,Dq
32+32 32q
DIVU.L <ea>,Dr:Dq
64 + 32 32r:32q
DIVUL.L <ea>,Dr:Dq
32 + 32 32r:32q
EOR
Source
Destination Destination
EOR Dn,<ea>
EORI
Immediate Data
Destination Destination
EORI #<data>,<ea>
EORI to CCR
Source
CCR CCR
EORI #<data>,CCR
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