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Электронный компонент: W3EG7234S262D3

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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7234S-D3
-JD3
-AJD3
December 2004
Rev. 2
PRELIMINARY*
256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL
DESCRIPTION
The W3EG7234S is a 32Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR
SDRAM component. The module consists of eighteen
32Mx4 DDR SDRAMs in 66 pin TSOP package
mounted on a 184 Pin FR4 substrate.
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
* This product is under development, is not qualifi ed or characterized and is subject to
change without notice.
FEATURES
Double-data-rate architecture
Clock speeds: 100MHz and 133MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power Supply: 2.5V 0.20V
JEDEC standard 184 pin DIMM package
Package height options:
JD3: 30.48mm (1.20")
AJD3: 28.70mm (1.13")
OPERATING FREQUENCIES
DDR266 @CL=2
DDR266 @CL=2.5
DDR200 @CL=2
Clock Speed
133MHz
133MHz
100MHz
CL-t
RCD
-t
RP
2-2-2
2.5-3-3
2-2-2
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7234S-D3
-JD3
-AJD3
December 2004
Rev. 2
PRELIMINARY
PIN CONFIGURATIONS
PIN NAMES
A0 A12
Address input (Multiplexed)
BA0-BA1
Bank Select Address
DQ0-DQ63
Data Input/Output
CB0-CB7
Check bits
DQS0-DQS17
Data Strobe Input/Output
CK0
Clock Input
CK0#
Clock Input
CKE0
Clock Enable Input
CS0#
Chip select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
V
CC
Power Supply
V
CCQ
Power Supply for DQS
V
SS
Ground
V
REF
Power Supply for Reference
V
CCSPD
Serial EEPROM Power Supply
SDA
Serial data I/O
SCL
Serial clock
SA0-SA2
Address in EEPROM
V
CCID
V
CC
Identifi cation Flag
NC
No Connect
RESET#
Reset Enable
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
1
V
REF
47
DQS8
93
V
SS
139
V
SS
2
DQ0
48
A0
94
DQ4
140
DQS17
3
V
SS
49
CB2
95
DQ5
141
A10
4
DQ1
50
V
SS
96
V
CCQ
142
CB6
5
DQS0
51
CB3
97
DQS9
143
V
CCQ
6
DQ2
52
BA1
98
DQ6
144
CB7
7
V
CC
53
DQ32
99
DQ7
145
V
SS
8
DQ3
54
V
CCQ
100
V
SS
146
DQ36
9
NC
55
DQ33
101
NC
147
DQ37
10
RESET#
56
DQS4
102
NC
148
V
CC
11
V
SS
57
DQ34
103
NC
149
DQS13
12
DQ8
58
V
SS
104
V
CCQ
150
DQ38
13
DQ9
59
BA0
105
DQ12
151
DQ39
14
DQS1
60
DQ35
106
DQ13
152
V
SS
15
V
CCQ
61
DQ40
107
DQS10
153
DQ44
16
*CK1
62
V
CCQ
108
V
CC
154
RAS#
17
*CK1#
63
WE#
109
DQ14
155
DQ45
18
V
SS
64
DQ41
110
DQ15
156
V
CCQ
19
DQ10
65
CAS#
111
*CKE1
157
CS0#
20
DQ11
66
V
SS
112
V
CCQ
158
*CS1#
21
CKE0
67
DQS5
113
*BA2
159
DQS14
22
V
CCQ
68
DQ42
114
DQ20
160
V
SS
23
DQ16
69
DQ43
115
A12
161
DQ46
24
DQ17
70
V
CC
116
V
SS
162
DQ47
25
DQS2
71
*CK2#
117
DQ21
163
*CS3#
26
V
SS
72
DQ48
118
A11
164
V
CCQ
27
A9
73
DQ49
119
DQS11
165
DQ52
28
DQ18
74
V
SS
120
V
CC
166
DQ53
29
A7
75
*CK2#
121
DQ22
167
A13*
30
V
CCQ
76
*CK2
122
A8
168
V
CC
31
DQ19
77
V
CCQ
123
DQ23
169
DQS15
32
A5
78
DQS6
124
V
SS
170
DQ54
33
DQ24
79
DQ50
125
A6
171
DQ55
34
V
SS
80
DQ51
126
DQ28
172
V
CCQ
35
DQ25
81
V
SS
127
DQ29
173
NC
36
DQS3
82
V
CCID
128
V
CCQ
174
DQ60
37
A4
83
DQ56
129
DQS12
175
DQ61
38
V
CC
84
DQ57
130
A3
176
V
SS
39
DQ26
85
V
CC
131
DQ30
177
DQS16
40
DQ27
86
DQS7
132
V
SS
178
DQ62
41
A2
87
DQ58
133
DQ31
179
DQ63
42
V
SS
88
DQ59
134
CB4
180
V
CCQ
43
A1
89
V
SS
135
CB5
181
SA0
44
CB0
90
NC
136
V
CCQ
182
SA1
45
CB1
91
SDA
137
CK0
183
SA2
46
V
CC
92
SCL
138
CK0#
184
V
CCSPD
* Not Used
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7234S-D3
-JD3
-AJD3
December 2004
Rev. 2
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQS0
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
DQS9
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DQS11
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DQS12
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DQS13
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DQS14
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DQS16
RCS0#
DQS4
DQS1
DQS5
DQS2
DQS3
DQS15
DQS6
DQS7
DQ15
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
DQS8
DQS17
RAS#
CAS#
CKE0
BA0-BA1
A0-A12
CS0#
RCS0#
RBA0 - RBA1
RA0 - RA12
RRAS#
RCAS#
RCKE0
RWE#
BA0-BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE: DDR SDRAMs
WE#: DDR SDRAMs
R
E
G
I
S
T
E
R
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
V
SS
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS10
RESET#
PCK
PCK#
WE#
A0
Serial PD
A1
A2
SA0
SA1
SA2
SCL
SDA
WP
PLL
CK0
CK0#
SDRAM
REGISTER
V
SS
DDR SDRAM
V
CC
/V
CCQ
DDR SDRAM
DDR SDRAM
V
REF
V
CCSPD
SPD
NOTE: All resistor values are 22 ohms unless otherwise specifi ed
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7234S-D3
-JD3
-AJD3
December 2004
Rev. 2
PRELIMINARY
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 to 3.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
, V
CCQ
-1.0 to 3.6
V
Storage Temperature
T
STG
-55 to +150
C
Power Dissipation
P
D
27
W
Short Circuit Current
I
OS
50
mA
Note:
Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
ABSOLUTE MAXIMUM RATINGS
DC CHARACTERISTICS
0C
T
A
70C, V
CC
= 2.5V 0.2V
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
2.3
2.7
V
Supply Voltage
V
CCQ
2.3
2.7
V
Reference Voltage
V
REF
1.15
1.35
V
Termination Voltage
V
TT
1.15
1.35
V
Input High Voltage
V
IH
V
REF
+ 0.15
V
CCQ
+ 0.3
V
Input Low Voltage
V
IL
-0.3
V
REF
-0.15
V
Output High Voltage
V
OH
V
TT
+ 0.76
--
V
Output Low Voltage
V
OL
--
V
TT
-0.76
V
CAPACITANCE
T
A
= 25C. f = 1MHz, V
CC
= 2.5V
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
C
IN1
6.25
pF
Input Capacitance (RAS#,CAS#,WE#)
C
IN2
6.25
pF
Input Capacitance (CKE0)
C
IN3
6.25
pF
Input Capacitance (CK0#,CK0)
C
IN4
5.5
pF
Input Capacitance (CS0#)
C
IN5
6.25
pF
Input Capacitance (DQS0-DQS17)
C
IN6
13
pF
Input Capacitance (BA0-BA1)
C
IN7
6.25
pF
Data input/output capacitance (DQ0-DQ63)(DQS)
C
OUT
13
pF
Data input/output capacitance (CB0-CB7)
C
OUT
13
pF
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7234S-D3
-JD3
-AJD3
December 2004
Rev. 2
PRELIMINARY
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0C
T
A
70C, V
CCQ
= 2.5V 0.2V, V
CC
= 2.5V 0.2V
Includes PLL and Register Power

Parameter
Symbol
Rank 1
Conditions
DDR266@CL=2
Max
DDR266@CL=2.5
Max
DDR200@CL=2
Max
Units
Operating Current
I
DD0
One device bank; Active - Precharge; t
RC
= t
RC
(MIN); t
CK
= t
CK
(MIN); DQ,DM and
DQS inputs changing once per clock cycle;
Address and control inputs changing once
every two cycles.
2520
2385
2385
mA
Operating Current
I
DD1
One device bank; Active-Read-Precharge
Burst = 2; t
RC
= t
RC
(MIN); t
CK
= t
CK
(MIN);
l
OUT
= 0mA; Address and control inputs
changing once per clock cycle.
2700
2520
2520
mA
Precharge Power-
Down Standby Current
I
DD2P
All device banks idle; Power-down mode;
t
CK
= t
CK
(MIN); CKE = (low)
54
54
54
mA
Idle Standby Current
I
DD2F
CS# = High; All device banks idle;
t
CK
= t
CK
(MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. V
IN
= V
REF
for DQ, DQS
and DM.
1120
1030
1030
mA
Active Power-Down
Standby Current
I
DD3P
One device bank active; Power-Down
mode; t
CK
(MIN); CKE = (low)
450
360
360
mA
Active Standby Current
I
DD3N
CS# = High; CKE = High; One device
bank; Active-Precharge;t
RC
= t
RAS
(MAX);
t
CK
= t
CK
(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address
and other control inputs changing once per
clock cycle.
1210
1120
1120
mA
Operating Current
I
DD4R
Burst = 2; Reads; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle; t
CK
=
t
CK
(MIN); l
OUT
= 0mA.
2745
2610
2610
mA
Operating Current
I
DD4W
Burst = 2; Writes; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
t
CK
= t
CK
(MIN); DQ,DM and DQS inputs
changing once per clock cycle.
2700
2565
2565
mA
Auto Refresh Current
I
DD5
t
RC
= t
RC
(MIN)
3770
3680
3645
mA
Self Refresh Current
I
DD6
CKE
0.2V
329
311
346
mA
Operating Current
I
DD7A
Four bank interleaving Reads (BL=4)
with auto precharge with t
RC
=t
RC
(MIN);
t
CK
=t
CK
(MIN); Address and control inputs
change only during Active Read or Write
commands.
4860
4770
4770
mA