White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG7263S-D3

-JD3

-AJD3

April 2004
Rev. # 2

PRELIMINARY*

512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL

DESCRIPTION

The W3EG7263S is a 64Mx72 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
component. The module consists of eighteen 64Mx4 DDR
SDRAMs in 66 pin TSOP package mounted on a 184 Pin
FR4 substrate.

Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lenths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.

This product is under development, is not qualifi ed or characterized and is subject to
change without notice.

FEATURES

Double-data-rate architecture
Clock Speeds: 100MHz, 133MHz and 166MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power supply: V

: 2.5V ± 0.2V

JEDEC standard 184 pin DIMM package

Package height options:
JD3: 30.48mm (1.20") and
AJD3: 28.70mm (1.13")

OPERATING FREQUENCIES

DDR333 @CL=2.5

DDR266 @CL=2

DDR266 @CL=2.5

DDR200 @CL=2

Clock Speed

166MHz

133MHz

100MHz

CL-t

RCD

-t

2.5-3-3

2-2-2

2-3-3

2.5-3-3

2-2-2

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White Electronic Designs

W3EG7263S-D3

-JD3

-AJD3

April 2004
Rev. # 2

PRELIMINARY

PIN

SYMBOL

PIN

SYMBOL

PIN

SYMBOL

PIN

SYMBOL

REF

DQS8

139

DQ0

DQ4

140

DQS17

CB2

DQ5

141

A10

DQ1

CCQ

142

CB6

DQS0

CB3

DQS9

143

CCQ

DQ2

BA1

DQ6

144

CB7

DQ32

DQ7

145

DQ3

CCQ

100

146

DQ36

DQ33

101

147

DQ37

RESET#

DQS4

102

148

DQ34

103

149

DQS13

DQ8

104

CCQ

150

DQ38

DQ9

BA0

105

DQ12

151

DQ39

DQS1

DQ35

106

DQ13

152

CCQ

DQ40

107

DQS10

153

DQ44

CCQ

108

154

RAS#

WE#

109

DQ14

155

DQ45

DQ41

110

DQ15

156

CCQ

DQ10

CAS#

111

157

CS0#

DQ11

112

CCQ

158

CKE0

DQS5

113

159

DQS14

CCQ

DQ42

114

DQ20

160

DQ16

DQ43

115

A12

161

DQ46

DQ17

116

162

DQ47

DQS2

117

DQ21

163

DQ48

118

A11

164

CCQ

DQ49

119

DQS11

165

DQ52

DQ18

120

166

DQ53

121

DQ22

167

CCQ

122

168

DQ19

CCQ

123

DQ23

169

DQS15

DQS6

124

170

DQ54

DQ24

DQ50

125

171

DQ55

DQ51

126

DQ28

172

CCQ

DQ25

127

DQ29

173

DQS3

CCID

128

CCQ

174

DQ60

DQ56

129

DQS12

175

DQ61

DQ57

130

176

DQ26

131

DQ30

177

DQS16

DQ27

DQS7

132

178

DQ62

DQ58

133

DQ31

179

DQ63

DQ59

134

CB4

180

CCQ

135

CB5

181

SA0

CB0

136

CCQ

182

SA1

CB1

SDA

137

CK0

183

SA2

SCL

138

CK0#

184

CCSPD

PIN CONFIGURATION

A0-A12

Address input (Multiplexed)

BA0-BA1

Bank Select Address

DQ0-DQ63

Data Input/Output

CB0-CB7

Check bits

DQS0-DQS17

Data Strobe Input/Output

CK0

Clock Input

CK0#

Clock Input

CKE0

Clock Enable input

CS0#

Chip Select Input

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

Power Supply (2.5V)

CCQ

Power Supply for DQS (2.5V)

Ground

REF

Power Supply for Reference

CCSPD

Serial EEPROM Power Supply
(2.3V to 3.6V)

SDA

Serial data I/O

SCL

Serial clock

SA0-SA2

Address in EEPROM

CCID

Indentifi cation Flag

No Connect

RESET#

Reset Enable

PIN NAMES

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White Electronic Designs

W3EG7263S-D3

-JD3

-AJD3

April 2004
Rev. # 2

PRELIMINARY

FUNCTIONAL BLOCK DIAGRAM

Notes:

1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQSresistors: 22 Ohms

DQ4
DQ5
DQ6
DQ7

DQ0
DQ1
DQ2
DQ3

DQS0

DQ12
DQ13
DQ14

DQ8
DQ9

DQ10
DQ11

DQS9

DQ20
DQ21
DQ22
DQ23

DQ16
DQ17
DQ18
DQ19

DQS11

DQ28
DQ29
DQ30
DQ31

DQ24
DQ25
DQ26
DQ27

DQS12

DQ36
DQ37
DQ38
DQ39

DQ32
DQ33
DQ34
DQ35

DQS13

DQ44
DQ45
DQ46
DQ47

DQ40
DQ41
DQ42

DQ43

DQS14

DQ52
DQ53

DQ54
DQ55

DQ48
DQ49
DQ50
DQ51

DQ60

DQ61

DQ62

DQ63

DQS16

RS0A#

DQS4

DQS1

DQS5

DQS2

DQS3

DQS15

DQS6

DQS7

DQ15

CB4
CB5
CB6

CB7

DQS8

DQS17

RAS#
CAS#
CKE0

BA0-BA1
A0-A12

CS0#

RS0B#

RS0A#

RBA0 - RBA1

RA0 - RA12
RRAS#

RCAS
RCKE0A

RWE#

RCKE0B

BA0-BA1: SDRAMs DQ0-D17
A0-A12: SDRAMs DQ0-D17
RAS#: SDRAMs DQ0-D17
CAS#: SDRAMs DQ0-D17
CKE: SDRAMs DQ0-D8
CKE: SDRAMs DQ9-D17
WE#: SDRAMs DQ0-D17

R
E
G

S
T
E

VSS

DQS10

RESET#

PCK

PCK#

WE#

Serial PD

SA0

SA1

SA2

SCL

SDA

D0 - D17

REF

CCSPD

SPD

PLL

CK0

CK0#

SDRAM

DQ56
DQ57
DQ58

DQ59

DQ56
DQ57
DQ58

DQ59

DQS

I/O3
I/O2
I/O1
I/O0

DQS

I/O3
I/O2
I/O1
I/O0

DQS

I/O3
I/O2
I/O1
I/O0

DQS

I/O3
I/O2
I/O1
I/O0

DQS

I/O3
I/O2
I/O1
I/O0

DQS

I/O3
I/O2
I/O1
I/O0

DQS

I/O3
I/O2
I/O1

DQS

I/O3
I/O2
I/O1
I/O0

DQS

I/O3
I/O2
I/O1
I/O0

I/O0

CS#

DQS

I/O3
I/O2
I/O1
I/O0

D17

DQS

I/O3
I/O2
I/O1
I/O0

DQS

I/O3
I/O2
I/O1
I/O0

D10

DQS

I/O3
I/O2
I/O1
I/O0

D11

DQS

I/O3
I/O2
I/O1
I/O0

D12

DQS

I/O3
I/O2
I/O1
I/O0

D13

DQS

I/O3
I/O2
I/O1
I/O0

D14

DQS

I/O3
I/O2
I/O1
I/O0

D15

DQS

I/O3
I/O2
I/O1
I/O0

D16

CCQ

CS#

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG7263S-D3

-JD3

-AJD3

April 2004
Rev. # 2

PRELIMINARY

Parameter

Symbol

Value

Units

Voltage on any pin relative to V

, V

OUT

-0.5 - 3.6

Voltage on V

supply relative to V

, V

CCQ

-1.0 - 3.6

Storage Temperature

STG

-55 - +150

°C

Power Dissipation

Short Circuit Current

Note: Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded.

Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Min

Max

Unit

Supply Voltage

2.3

2.7

Supply Voltage

CCQ

2.3

2.7

Reference Voltage

REF

1.15

1.35

Termination Voltage

1.15

1.35

Input High Voltage

REF

+ 0.15

CCQ

+ 0.3

Input Low Voltage

-0.3

REF

- 0.15

Output High Voltage

+ 0.76

Output Low Voltage

- 0.76

Parameter

Symbol

Min

Max

Unit

Input Capacitance (A0-A12)

IN1

6.5

Input Capacitance (RAS#, CAS#, WE#)

IN2

6.5

Input Capacitance (CKE0)

IN3

6.5

Input Capacitance (CK0,CK0#)

IN4

5.5

Input Capacitance (CS0#)

IN5

6.5

Input Capacitance (DQM0-DQM8)

IN6

Input Capacitance (BA0-BA1)

IN7

6.5

Data input/output capacitance (DQ0-DQ63)(DQS)

OUT

Data input/output capacitance (CB0-CB7)

OUT

DC CHARACTERISTICS

0°C £ T

£ 70°C, V

= 2.5V ± 0.2V

CAPACITANCE

TA = 25°C, f = 1MHz, V

= 2.5V

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG7263S-D3

-JD3

-AJD3

April 2004
Rev. # 2

PRELIMINARY

SPECIFICATIONS AND TEST CONDITIONS

Recommended operating conditions, 0°C £ T

£ +70°C, V

CCQ

= 2.5V ± 0.2V, V

= 2.5V ± 0.2V.

Includes DDR SDRAM components and PLL and Register

Parameter

Symbol

Rank 1
Conditions

DDR333@CL=2.5

Max

DDR266:@CL=2, 2.5

Max

DDR200@CL=2 S

Max

Units

Rank 2

Standby

State

Operating Current

DD0

One device bank; Active - Precharge;
t

= t

(MIN); t

= t

(MIN); DQ,DM

and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.

TBD

1715

DD3N

Operating Current

DD1

One device bank; Active-Read-
Precharge Burst = 2; t

= t

(MIN);

= t

(MIN); l

OUT

= 0mA; Address

and control inputs changing once per
clock cycle.

TBD

2255

DD3N

Precharge Power-
Down Standby Current

DD2P

All device banks idle; Power-down
mode; t

= t

(MIN); CKE = (low)

TBD

rnA

DD2P

Idle Standby Current

DD2F

CS# = High; All device banks idle;
t

= t

(MIN); CKE = High; Address

and other control inputs changing once
per clock cycle. V

= V

REF

for DQ, DQS

and DM.

TBD

671

DD2F

Active Power-Down
Standby Current

DD3P

One device bank active; Power-Down
mode; t

(MIN); CKE = (low)

TBD

540

DD3P

Active Standby Current

DD3N

CS# = High; CKE = High; One device
bank; Active-Precharge;t

= t

RAS

(MAX); t

= t

(MIN); DQ, DM and

DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.

TBD

1121

DD3N

Operating Current

DD4R

Burst = 2; Reads; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; t

= t

(MIN); l

OUT

= 0mA.

TBD

2795

DD3N

Operating Current

DD4W

Burst = 2; Writes; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; t

= t

(MIN); DQ,DM and DQS

inputs changing once per clock cycle.

TBD

2795

rnA

DD3N

Auto Refresh Current

DD5

= t

(MIN)

TBD

3281

DD3N

Self Refresh Current

DD6

CKE £ 0.2V

TBD

365

DD6

Operating Current

DD7A

Four bank interleaving Reads (BL=4)
with auto precharge with t

(MIN);

(MIN); Address and control

inputs change only during Active Read
or Write commands.

TBD

5315

DD3N

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG7263S-D3

-JD3

-AJD3

April 2004
Rev. # 2

PRELIMINARY

DD1

: OPERATING CURRENT: ONE BANK

1. Typical Case: V

= 2.5V, T = 25°C

2. Worst Case: V

= 2.7V, T = 10°C

3. Only one bank is accessed with t

(min), Burst

Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. l

OUT

= 0mA

4. Timing patterns

· DDR200 (100MHz, CL = 2) : t

= 10ns, CL2, BL =

4, t

RCD

= 2*t

, t

RAg

= 5*t

Read: A0 N R0 N N P0 N A0 N - repeat the same
timing with random address changing; 50% of data
changing at every burst

· DDR266 (133MHz, CL = 2.5) : t

= 7.5ns, CL = 2.5,

BL = 4, t

RCD

= 3*t

, t

= 9*t

, t

RAg

= 5*t

Read: A0 N N R0 N P0 N N N A0 N - repeat the

same timing with random address changing; 50% of
data changing at every burst

· DDR266 (133MHz, CL = 2) : t

= 7.5ns, CL = 2, BL

= 4, t

RCD

= 3*t

, t

= 9*t

, t

RAg

= 5*t

Read: A0 N N R0 N P0 N N N A0 N - repeat the

same timing with random address changing; 50% of
data changing at every burst

· DDR333 (166MHz, CL = 2.5) : t

= 6ns, BL = 4,

RCD

= 10*t

, t

RAg

= 7*t

Read: A0 N N R0 N P0 N N N A0 N -- repeat the

same timing with random address changing; 50% of
data changing at every burst

DD7A

: OPERATING CURRENT: FOUR BANKS

1. Typical Case: V

= 2.5V, T = 25°C

2. Worst Case: V

= 2.7V, T = 10°C

3. Four banks are being interleaved with t

(min), Burst

Mode, Address and Control inputs on NOP edge are
not changing.
lout = 0mA

4. Timing patterns

· DDR200 (100MHz, CL = 2) : t

= 10ns, CL2, BL =

4, t

RRD

= 2*t

, t

RCD

= 3*t

, Read with autoprecharge

Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0

- repeat the same timing with random address
changing; 100% of data changing at every burst

· DDR266 (133MHz, CL = 2.5) : t

= 7.5ns, CL

= 2.5, BL = 4, t

RRD

= 3*t

, t

RCD

= 3*t

Read with

autoprecharge

Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1

R0 - repeat the same timing with random address
changing; 100% of data changing at every burst

· DDR266 (133MHz, CL = 2): t

= 7.5ns, CL2 = 2,

BL = 4, t

RRD

= 2*t

, t

RCD

= 3*t

Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1

R0 - repeat the same timing with random address
changing; 100% of data changing at every burst

· DDR333 (166MHz, CL = 2.5) : t

= 6ns, BL = 4,

RRD

= 3*t

, t

RCD

= 3*t

, Read with autoprecharge

Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1

R0 - repeat the same timing with random address
changing; 100% of data changing at every burst

Legend: A = Activate, R = Read, W = Write, P =
Precharge, N = NOP

DETAILED TEST CONDITIONS FOR DDR SDRAM I

DD1

& I

DD7A

A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG7263S-D3

-JD3

-AJD3

April 2004
Rev. # 2

PRELIMINARY

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS

Notes 1-5, 7; notes appear following parameter tables; 0°C T

+70°C; V

= +2.5V ±0.2V, V

CCQ

= +2.5V ±0.2V

AC Characteristics

335

262/263/265

202

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Units

Notes

Access window of DQs from CK, CK#

-0.7

+0.7

-0.75

+0.75

-0.8

+0.8

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

Clock cycle time

CL=2.5

(2.5)

7.5

CL=2

(2)

7.5

7.5/10

DQ and DM input hold time relative to DQS

0.45

0.5

0.6

14,17

DQ and DM input setup time relative to DQS

0.45

0.5

0.6

14,17

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK, CK#

DQSCK

-0.60

+0.60

-0.75

+0.75

-0.8

+0.8

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.35

0.5

0.6

13,14

Write command to fi rst DQS latching transition

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

, t

Data-out high-impedance window from CK, CK#

+0.70

+0.75

+0.8

8,19

Data-out low-impedance window from CK, CK#

-0.70

-0.75

-0.8

8,20

Address and control input hold time (fast slew rate)

IHf

0.75

0.90

1.1

Address and control input set-up time (fast slew rate)

ISf

0.75

0.90

1.1

Address and control input hold time (slow slew rate)

IHs

0.80

1.1

Address and control input setup time (slow slew rate)

ISs

0.80

1.1

Address and control input pulse width (for each input)

IPW

2.2

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to fi rst DQ to go non-valid, per access

-t

QHS

-t

QHS

-t

QHS

13,14

Data hold skew factor

QHS

0.50

0.75

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG7263S-D3

-JD3

-AJD3

April 2004
Rev. # 2

PRELIMINARY

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS (continued)

Notes 1-5, 7; notes appear following parameter tables; 0°C T

+70°C; V

= +2.5V ±0.2V, V

CCQ

= +2.5V ±0.2V

AC Characteristics

335

262/263/265

202

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Units

Notes

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

10,11

DQS write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window

-t

DQSQ

-t

DQSQ

-t

DQSQ

REFRESH to REFRESH command interval

REFC

70.3

Average periodic refresh interval

REFI

7.8

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

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White Electronic Designs

W3EG7263S-D3

-JD3

-AJD3

April 2004
Rev. # 2

PRELIMINARY

12. The refresh period is 64ms. This equates to an average refresh

rate of 15.625µs (256Mb component) or 7.8125µs (512 Mb
component). However, an AUTO REFRESH command must be
asserted at least once every 140.6µs (256 Mb component) or
70.3µs (512Mb component); burst refreshing or posting by the
DRAM controller greater than eight refresh cycles is not allowed.

13. The valid data window is derived by achieving other specifi cations

- t

CK/2

), t

DQSQ

, and t

= t

- t

QHS

). The data valid window

derates directly proportional with the clock duty cycle and a
practical data valid window can be derived. The clock is allowed
a maximum duty cycled variation of 45/55. Functionality is
uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.

14. Referenced to each output group: x4 = DQS with DQ0-DQ4.

15. READs and WRITEs with auto precharge are not allowed to be

issued until t

RAS

(MIN) can be satisfi ed prior to the internal precharge

command being issued.

16. JEDEC specifi es CK and CK# input slew rate must be > 1V/ns

(2V/ns differentially).

17. DQ and DM input slew rates must not deviate from DQS by more

than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to t

and t

for

each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.

18. t

min is the lesser of t

min and t

min actually applied to the

device CK and CK# inputs, collectively during bank active.

19. This maximum value is derived from the referenced test load. In

practice, the values obtained in a typical terminated design may
refl ect up to 310ps less for t

(MAX) and last DVW. t

(MAX) will

prevail over the t

DQSCK

(MAX) + t

RPST

(MAX) condition. t

(MIN) will

prevail over t

DQSCK

(MIN) + PRE (MAX) condition.

20. For slew rates greater than 1V/ns the (LZ) transition will start about

310ps earlier.

21. CKE must be active (High) during the entire time a refresh

command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until t

REF

later.

22. Whenever the operating frequency is altered, not including jitter,

the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).

Notes

All voltages referenced to V

Tests for AC timing, I

, and electrical AC and DC characteristics

may be conducted at normal reference / supply voltage levels, but
the related specifi cations and device operations are guaranteed for
the full voltage range specifi ed.

Outputs are measured with equivalent load:

4. AC

timing

and

tests may use a V

-to-V

swing of up to 1.5V in

the test environment, but input timing is still referenced to V

REF

(or

to the crossing point for CK/CK#), and parameter specifi cations
are guaranteed for the specifi ed AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between V

(AC) and V

(AC).

The AC and DC input level specifi cations are defi ned in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).

Command/Address input slew rate = 0.5V/ns. For -75 with slew
rates 1V/ns and faster, t

and t

are reduced to 900ps. If the

slew rate is less than 0.5V/ns, timing must be derated: t

has an

additional 50ps per each 100mV/ns reduction in slew rate from the
500mV/ns. t

has 0ps added, that is, it remains constant. If the

slew rate exceeds 4.5V/ns, functionality is uncertain.

Inputs are not recognized as valid until V

REF

stabilizes. Exception:

during the period before V

REF

stabilizes, CKE £ 0.3 x V

CCQ

recognized as LOW.

8. t

and t

transitions occur in the same access time windows as

valid data transitions. These parameters are not referenced to a
specifi c voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).

The maximum limit for this parameter is not a device limit. The
device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.

10. This is not a device limit. The device will operate with a negative

value, but system performance could be degraded due to bus
turnaround.

11.

It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
high during this time, depending on t

DQSS

Output

Output
(V

OUT

)

Reference

Point

30pF

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