1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W78M32V-XBX
April 2006
Rev. 3
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write
Operation Multi-Chip Package
Access Times of 70, 90, 100, 120ns
Packaging
159 PBGA, 13x22mm 1.27mm pitch
1,000,000 Erase/Program Cycles per sector
Page Mode
Page size is 8 words: Fast page read access from
random locations within the page.
Sector Architecture
Bank A (16Mb): 4Kw x 8 and 32 Kw x 31
Bank B (48Mb): 32Kw x 96
Bank C (48Mb): 32Kw x 96
Bank D (16Mb): 4Kw x 8 and 3Kw x 31
Both top and bottom boot blocks
Zero Power Operation
Organized as 8Mx32, user confi gurable as 2x8Mx16
Commercial, Industrial and Military Temperature
Ranges
3.3 Volt for read, erase and write operations
Simultaneous read/write operations:
Data can be continuously read from one bank
while executing erase/program functions in
another bank
Zero latency between read and write operations
Erase Suspend/Resume
Suspends erase operations to allow read or
programming in other sectors of same bank
Data Polling and Toggle Bits
Provides a software method of detecting the status
of program or erase cycles
Unlock Bypass Program command
Reduces overall programming time when issuing
multiple program command sequences
Ready/Busy# output (RY/BY#)
Hardware method for detecting program or erase
cycle completion
Hardware reset pin (RESET#)
Hardware method of resetting the internal state
machine to the read mode
WP#/ACC input pin
Write protect (WP#) function allows protection of
two outermost boot sector, regardless of sector
protect status
Acceleration (ACC) function accelerates program
timing
Persistent Sector Protection
A command sector protection method of locking
combinations of individual sectors and sector
groups to prevent program or erase operation
within that sector
Password Sector Protection or Cancellation
A sector protection method to lock combinations
of individual sectors and sector groups to prevent
program or erase operations within that sector
using a user-defi ned 64-bit password.
* This product is subject to change without notice.
FEATURES
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W78M32V-XBX
April 2006
Rev. 3
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
WE1#
WE2#
CS2#
CS1#
RY/BY#
RESET#
OE#
A
0-22
WP#/ACC
DQ
16-31
DQ
0-15
8M X 16
8M X 16
V
IO
V
IO
V
CC
GND
GND
GND
GND
GND
GND
V
IO
V
CC
V
IO
V
CC
V
IO
GND
GND
DQ17
DQ24
DQ16
CS
2
#
OE#
A2
A3
A4
NC
NC
NC
NC
V
CC
GND
GND
DQ25
DQ27
DQ19
DQ26
DQ18
A0
WP#/A
CC
A6
A17
NC
NC
NC
NC
NC
GND
GND
WE
2
#
DQ29
DQ21
DQ28
DQ20
A22
A11
A9
RY/BY#
NC
NC
NC
NC
NC
GND
V
CC
V
CC
V
CC
VIO
V
IO
DQ31
DQ23
DQ30
DQ22
V
CC
GND
V
CC
GND
DNU*
NC
NC
NC
NC
V
IO
NC
NC
NC
NC
NC
A12
V
IO
GND
A14
DQ9
DQ1
DQ8
DQ0
CS
1
#
V
CC
GND
DNU
NC
NC
NC
NC
A16
A7
A1
A5
DQ4
DQ11
DQ3
DQ10
DQ2
GND
GND
NC
NC
NC
NC
NC
A21
A10
RESET#
A18
WE
1
#
DQ6
DQ13
DQ5
DQ12
GND
GND
V
CC
NC
NC
NC
NC
A20
A15
A13
A8
A19
DQ15
DQ7
DQ14
GND
GND
V
IO
V
CC
V
IO
V
CC
GND
GND
GND
GND
GND
GND
V
IO
V
CC
V
IO
V
CC
V
IO
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1
2
3
4
5
6
7
8
9 10
BLOCK DIAGRAM
PIN DESCRIPTION
DQ
0-31
Data Inputs/Outputs
A
0-22
Address Inputs
WE#
1-2
Write Enables
CS#
1-2
Chip Selects
OE#
Output Enable
RESET#
Hardware Reset
WP#/ACC
Hardware Write
Protection/Acceleration
RY/BY#
Ready/Busy Output
V
CC
Power Supply
V
IO
I/O Power Supply
GND
Ground
DNU
Do Not Use
NC
Not Connected
FIG 1: PIN CONFIGURATION
FOR W78M32V-XBX (TOP VIEW)
*Ball L5 is reserved for A23 on future upgrades
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W78M32V-XBX
April 2006
Rev. 3
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
GENERAL DESCRIPTION
The W78M32V-XBX is a 256Mb, 3.3 volt-only Page Mode
and Simultaneous Read/Write Flash memory device.
The device offers fast page access times allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has separate chip
enable (CS#), write enable (WE#) and output enable (OE#)
controls. Simultaneous Read/Write Operation with Zero
Latency.
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory space
into 4 banks, which can be considered to be four separate
memory arrays as far as certain operations are concerned.
The device can improve overall system performance by
allowing a host system to program or erase in one bank,
then immediately and simultaneously read from another
bank with zero latency (with two simultaneous operations
operating at any one time). This releases the system from
waiting for the completion of a program or erase operation,
greatly improving system performance.
The device can be organized in both top and bottom sector
confi gurations. The banks are organized as follows:
JEDEC 42.4 single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register contents
serve as inputs to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar
to reading from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. The Unlock Bypass mode facilitates
faster programming times by requiring only two write cycles
to program data instead of four. Device erasure occurs by
executing the erase command sequence.
The host system can detect whether a program or erase
operation is complete by reading the DQ7 (Data# Polling)
and DQ6 (toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors to
be erased and reprogrammed without affecting the data
contents of other sectors.
Hardware data protection measures include a low
V
CC
detector that automatically inhibits write operations
during power transitions. The hardware sector protection
feature disables both program and erase operations in any
combination of sectors of memory. This can be achieved
in-system or via programming equipment.
The Erase Suspend/Erase Resume feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If
a read is needed from the SecSi Sector area (One Time
Program area) after an erase suspend, then the user must
use the proper command sequence to enter and exit this
region.
The device offers two power-saving features. When
addresses have been stable for a specifi ed amount of time,
the device enters the automatic sleep mode. The system
can also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.
Bank Sectors
A
16 Mbit (4 Kw x 8 and 32 Kw x 31)
B
48 Mbit (32 Kw x 96)
C
48 Mbit (32 Kw x 96)
D
16 Mbit (4 Kw x 8 and 32 Kw x 31)
Page Mode Features
The page size is 8 words. After initial page access is
accomplished, the page mode operation provides fast read
access speed of random locations within that page.
Standard Flash Memory
Features
The device requires a 3.3 volt power supply for both read and
write functions. Internally generated and regulated voltages
are provided for the program and erase operations.
The device is entirely command set compatible with the
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W78M32V-XBX
April 2006
Rev. 3
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is a latch used to store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs
to the internal state machine. The state machine outputs
dictate the function of the device.
Table 1
lists the device
bus operations, the inputs and control levels they require,
and the resulting output. The following subsections describe
each of these operations in further detail.
TABLE 1. DEVICE BUS OPERATION
3
Operation
CS#
OE#
WE#
RESET#
WP#/ACC
Addresses
(A22-A0)
DQ15-DQ0
Read
L
L
H
H
X
A
IN
D
OUT
Write
L
H
L
H
X
A
IN
D
IN
Standby
V
IO
0.3 V
X
X
V
IO
0.3 V
X (Note 2)
X
High-Z
Output Disable
L
H
H
H
X
X
High-Z
Reset
X
X
X
L
X
X
High-Z
Temporary Sector Unprotect (High
Voltage
X
X
X
V
ID
X
A
IN
D
IN
Legend: L = Logic Low = V
IL
, H = Logic High = V
IH,
V
ID
= 11.5-12.5 V, V
HH
= 8.5-9.5 V, X = Don't Care, SA = Sector Address, A
IN
= Address In, D
IN
= Data In,
D
OUT
= Data Out
Notes:
1.
The sector protect and sector unprotect functions may also be Implemented via programming equipment. See the High Voltage Sector Protection section.
2.
WP#/ACC must be high when writing to sectors 0, 1, 268, or 269.
3.
For each chip
REQUIREMENTS FOR READING
ARRAY DATA
To read array data from the outputs, the system must drive
the OE# and appropriate CS# pins to V
IL
. CS# is the power
control. OE# is the output control and gates array data to
the output pins. WE# should remain at V
IH.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures
that no spurious alteration of the memory content occurs
during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device
address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until
the command register contents are altered.
Refer to the
AC Characteristics
table for timing specifi cations
and to Figure 11 for the timing diagram. I
CC1
in the
DC Characteristics table represents the active current
specifi cation for reading array data.
Random Read (Non-Page Read)
Address access time (t
ACC
) is equal to the delay from stable
addresses to valid output data. The chip enable access
time (t
CS
) is the delay from the stable addresses and stable
CS# to valid data at the output inputs. The output enable
access time is the delay from the falling edge of the OE#
to valid data at the output inputs (assuming the addresses
have been stable for at least t
ACC
t
OE
time).
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read operation.
This mode provides faster read access speed for random
locations within a page. Address bits A22A3 select an 8
word page, and address bits A2A0 select a specifi c word
within that page. This is an asynchronous operation with the
microprocessor supplying the specifi c word location.
The random or initial page access is t
ACC
or t
CS
and
subsequent page read accesses (as long as the locations
specifi ed by the microprocessor falls within that page) is
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W78M32V-XBX
April 2006
Rev. 3
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
equivalent to t
PACC
. When CS# is deasserted (CS#=V
IH
),
the reassertion of CS# for subsequent access has access
time of t
ACC
or t
CS
. Here again, CS# selects the device and
OE# is the output control and should be used to gate data
to the output inputs if the device is selected. Fast page
mode accesses are obtained by keeping A22A3 constant
and changing A2A0 to select the specifi c word within that
page.
The device features an Unlock Bypass mode to facilitate
faster programming. Once a bank enters the Unlock Bypass
mode, only two write cycles are required to program a word,
instead of four. The "Word Program Command Sequence"
section has details on programming data to the device using
both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors,
or the entire device.
Table 4
indicates the address space
that each sector occupies. A "bank address" is the address
bits required to uniquely select a bank. Similarly, a "sector
address" refers to the address bits required to uniquely
select a sector. The "Command Defi nitions" section has
details on erasing a sector or the entire chip, or suspending/
resuming the erase operation.
I
CC2
in the DC Characteristics table represents the
active current specifi cation for the write mode. The
AC
Characteristics
section contains timing specifi cation tables
and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations through
the A
CC
function. This function is primarily intended to allow
faster manufacturing throughput at the factory.
If the system asserts V
HH
on this pin, the device automatically
enters the mentioned Unlock Bypass mode, temporarily
unprotects any protected sectors, and uses the higher
voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program
command sequence as required by the Unlock Bypass
mode. Removing V
HH
from the WP#/ACC pin returns the
device to normal operation. Note that V
HH
must not be
asserted on WP#/ACC for operations other than accelerated
programming, or device damage may result. In addition,
the WP#/ACC pin should be raised to V
CC
when not in
use. That is, the WP#/ACC pin should not be left fl oating
or unconnected; inconsistent behavior of the device may
result.
Autoselect Functions
If the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on DQ63DQ0. Standard
read cycle timings apply in this mode. Refer to the
Autoselect
Mode
and
Autoselect Command Sequence
sections for
more information.
TABLE 2. PAGE SELECT
Word
A2
A1
A0
Word 0
0
0
0
Word 1
0
0
1
Word 2
0
1
0
Word 3
0
1
1
Word 4
1
0
0
Word 5
1
0
1
Word 6
1
1
0
Word 7
1
1
1
SIMULTANEOUS OPERATION
In addition to the conventional features (read, program,
erase-suspend read, and erase-suspend program), the
device is capable of reading data from one bank of memory
while a program or erase operation is in progress in another
bank of memory (simultaneous operation). The bank can be
selected by bank addresses (A22A20) with zero latency.
The simultaneous operation can execute multi-function
mode in the same bank.
TABLE 3. BANK SELECT
Bank
A22-A20
Bank A
000
Bank B
001, 010, 011
Bank C
100, 101, 110
Bank D
111
WRITING COMMANDS/COMMAND
SEQUENCES
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE# and CS# to V
IL
, and
OE# to V
IH
.
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