W27C257
32K
8 ELECTRICALLY ERASABLE EPROM
Publication Release Date: September 1998
- 1 -
Revision A2
GENERAL DESCRIPTION
The W27C257 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 32768
8 bits that operates on a single 5 volt power supply. The W27C257
provides an electrical chip erase function. This part was the same EPROM Writer's utilities as the
W27E257.
FEATURES
High speed access time:
100/120 nS (max.)
Read operating current: 30 mA (max.)
Erase/Programming operating current
30 mA (max.)
Standby current: 1 mA (max.)
Single 5V power supply
+14V erase/+12V programming voltage
Fully static operation
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available packages: 28-pin 600 mil DIP and
32-pin PLCC
PIN CONFIGURATIONS
A6
A5
A4
A3
A2
A1
A0
NC
Q0
5
6
7
8
9
10
11
12
13
1
4
4 3 2 1 3
2
3
1
3
0 29
28
27
26
25
24
23
22
21
32-pin
PLCC
Q
1
Q
2
N
C
Q
3
Q
4
Q
5
G
N
D
26
27
28
1
2
3
4
5
6
7
8
21
22
23
24
25
16
17
18
19
20
9
10
11
12
13
14
15
Q3
CE
Q7
Q6
Q5
Q4
A9
A11
OE
A10
A14
A13
A8
1
5
1
6
1
7
1
8
1
9
2
0
GND
Q2
Q1
A0
A1
A2
A3
A4
A5
A6
A7
A12
V
Q0
PP
V
CC
A
7
N
C
A
1
2
V
P
P
A
1
4
A
1
3
V
C
C
A8
A9
A11
NC
OE
A10
Q7
CE
Q6
28-pin
DIP
BLOCK DIAGRAM
CE
OE
CONTROL
OUTPUT
BUFFER
DECODER
CORE
ARRAY
Q0
Q7
.
.
A0
.
.
A14
V
GND
CC
V
PP
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
-
A14
Address Inputs
Q0
-
Q7
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
V
PP
Program/Erase Supply Voltage
V
CC
Power Supply
GND
Ground
NC
No Connection
W27C257
- 2 -
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27C257 has two control functions, both of which produce data
at the outputs.
CE is for power control and chip select. OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (T
ACC
) is equal to the delay from CE to output
(T
CE
), and data are available at the outputs T
OE
after the falling edge of OE , if T
ACC
and T
CE
timings
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27C257 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when V
PP
is raised to V
PE
(14V), V
CC
= V
CE
(5V), OE = V
IH
(2V or above but
lower than V
CC
), A9 = V
HH
(14V), A0 = V
IL
(0.8V or below but higher than GND), and all other
address pins equal V
IL
and data input pins equal V
IH
. Pulsing CE low starts the erase operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if V
PP
= V
PE
(14V), CE = V
IH
, and OE =
V
IL
.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when V
PP
is raised to V
PP
(12V), V
CC
= V
CP
(5V), OE = V
IH
, the address pins equal the desired address, and the input pins
equal the desired inputs. Pulsing CE low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether or not they have been successfully
programmed with the desired data. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if V
PP
= V
PP
(12V), CE = V
IH
,
and OE = V
IL
.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE = V
IH
, erasing or programming of non-target chips is inhibited, so that except for the
CE and OE pins, the W27C257 may have common inputs.
W27C257
Publication Release Date: September 1998
- 3 -
Revision A2
Standby Mode
The standby mode significantly reduces V
CC
current. This mode is entered when CE = V
IH
. In
standby mode, all outputs are in a high impedance state, independent of OE .
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27C257 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (I
SB
), active current levels (I
CC
), and
transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1
F ceramic capacitor connected between its V
CC
and GND. This high frequency, low inherent-
inductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7
F electrolytic capacitor should be placed at the array's power supply connection
between V
CC
and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
TABLE OF OPERATING MODES
(V
PP
= 12V, V
PE
= 14V, V
HH
= 12V, V
CP
= 5V, X = V
IH
or V
IL
)
MODE
PINS
CE
OE
A0
A9
V
CC
V
PP
OUTPUTS
Read
V
IL
V
IL
X
X
V
CC
V
CC
D
OUT
Output Disable
V
IL
V
IH
X
X
V
CC
V
CC
High Z
Standby (TTL)
V
IH
X
X
X
V
CC
V
CC
High Z
Standby (CMOS)
V
CC
0.3V
X
X
X
V
CC
V
CC
High Z
Program
V
IL
V
IH
X
X
V
CP
V
PP
D
IN
Program Verify
V
IH
V
IL
X
X
V
CP
V
PP
D
OUT
Program Inhibit
V
IH
V
IH
X
X
V
CP
V
PP
High Z
Erase
V
IL
V
IH
V
IL
V
PE
V
CC
V
PE
D
IH
Erase Verify
V
IH
V
IL
X
X
V
CC
V
PE
D
OUT
Erase Inhibit
V
IH
V
IH
X
X
V
CP
V
PP
High Z
Product Identifier-manufacturer
V
IL
V
IL
V
IL
V
HH
V
CC
V
CC
DA (Hex)
Product Identifier-device
V
IL
V
IL
V
IH
V
HH
V
CC
V
CC
02 (Hex)
W27C257
- 4 -
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Ambient Temperature with Power Applied
-55 to +125
C
Storage Temperature
-65 to +125
C
Voltage on all pins with Respect to Ground Except V
PP,
A9
and V
CC
pins
-0.5 to V
CC
+0.5
V
Voltage on V
PP
Pin with Respect to Ground
-0.5 to +14.5
V
Voltage on A9 Pin with Respect to Ground
-0.5 to +14.5
V
Voltage on V
CC
Pin with Respect to Ground
-0.5 to +7
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC Erase Characteristics
(T
A
= 25
C
5
C, V
CC
= 5.0V
5%)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Input Load Current
I
LI
V
IN
= V
IL
or V
IH
-10
-
10
A
V
CC
Erase Current
I
CP
CE = V
IL
-
-
30
mA
V
PP
Erase Current
I
PP
CE = V
IL
-
-
30
mA
Input Low Voltage
V
IL
-
-0.3
-
0.8
V
Input High Voltage
V
IH
-
2.4
-
5.5
V
Output Low Voltage (Verify)
V
OL
I
OL
= 2.1 mA
-
-
0.45
V
Output High Voltage (Verify)
V
OH
I
OH
= -0.4 mA
2.4
-
-
-
A9 Erase Voltage
V
ID
-
13.75
14
14.25
V
V
PP
Erase Voltage
V
PE
-
13.75
14
14.25
V
V
CC
Supply Voltage (Erase)
V
CE
-
4.5
5.0
5.5
V
Note: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
CAPACITANCE
(V
CC
= 5V, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Output Capacitance
C
OUT
V
OUT
= 0V
12
pF
W27C257
Publication Release Date: September 1998
- 5 -
Revision A2
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
10 nS
Input and Output Timing Reference Level
0.8V/2.0V
Output Load
C
L
= 100 pF, I
OH
/I
OL
= -0.4 mA/2.1 mA
AC Test Load and Waveform
+1.3V
3.3K ohm
100 pF (Including Jig and Scope)
D
(IN914)
OUT
Input
2.4V
0.45V
2.0V
0.8V
2.0V
0.8V
Test Points
Test Points
Output
W27C257
- 6 -
READ OPERATION DC CHARACTERISTICS
(V
CC
= 5.0V
5%, T
A
= 0 to 70
C)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Input Load Current
I
LI
V
IN
= 0V to V
CC
-5
-
5
A
Output Leakage Current
I
LO
V
OUT
= 0V to V
CC
-10
-
10
A
V
CC
Standby Current
I
SB
CE = V
IH
-
-
1.0
mA
I
SB1
CE = V
CC
0.2V
-
5
100
A
V
CC
Operating Current
I
CC
CE = V
IL
I
OUT
= 0 mA
f = 5 MHz
-
-
30
mA
V
PP
Operating Current
I
PP
V
PP
= V
CC
-
-
100
A
Input Low Voltage
V
IL
-
-0.3
-
0.8
V
Input High Voltage
V
IH
-
2.2
-
V
CC
+0.5
V
Output Low Voltage
V
OL
I
OL
= 2.1 mA
-
-
0.45
V
Output High Voltage
V
OH
I
OH
= -0.4 mA
2.4
-
-
V
V
PP
Operating Voltage
V
PP
-
V
CC
-0.7
-
V
CC
V
READ OPERATION AC CHARACTERISTICS
(V
CC
= 5.0V
5%, T
A
= 0 to 70
C)
PARAMETER
SYM.
W27C257-10
W27C257-12
UNIT
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
T
RC
100
-
120
-
nS
Chip Enable Access Time
T
CE
-
100
-
120
nS
Address Access Time
T
ACC
-
100
-
120
nS
Output Enable Access Time
T
OE
-
50
-
60
nS
OE High to High-Z Output
T
DF
-
30
-
30
nS
Output Hold from Address
Change
T
OH
0
-
0
-
nS
Note: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
W27C257
Publication Release Date: September 1998
- 7 -
Revision A2
DC PROGRAMMING CHARACTERISTICS
(V
CC
= 5.0V
5%, T
A
= 25
C
5
C)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Input Load Current
I
LI
V
IN
= V
IL
or V
IH
-10
-
10
A
V
CC
Program Current
I
CP
CE = V
IL
-
-
30
mA
V
PP
Program Current
I
PP
CE = V
IL
-
-
30
mA
Input Low Voltage
V
IL
-
-0.3
-
0.8
V
Input High Voltage
V
IH
-
2.4
-
5.5
V
Output Low Voltage (Verify)
V
OL
I
OL
= 2.1 mA
-
-
0.45
V
Output High Voltage (Verify)
V
OH
I
OH
= -0.4 mA
2.4
-
-
V
A9 Silicon I.D. Voltage
V
ID
-
11.5
12.0
12.5
V
V
PP
Program Voltage
V
PP
-
11.75
12.0
12.25
V
V
CC
Supply Voltage (Program)
V
CP
-
4.5
5.0
5.5
V
AC PROGRAMMING/ERASE CHARACTERISTICS
(V
CC
= 5.0V
5%, T
A
= 25
C
5
C)
PARAMETER
SYM.
LIMITS
UNIT
MIN.
TYP.
MAX.
V
PP
Setup Time
T
VPS
2.0
-
-
S
Address Setup Time
T
AS
2.0
-
-
S
Data Setup Time
T
DS
2.0
-
-
S
CE Program Pulse Width
T
PWP
95
100
105
S
CE Erase Pulse Width
T
PWE
95
100
105
mS
Data Hold Time
T
DH
2.0
-
-
S
OE Setup Time
T
OES
2.0
-
-
S
Data Valid from OE
T
OEV
-
-
150
nS
OE High to Output High Z
T
DFP
0
-
130
nS
Address Hold Time
T
AH
0
-
-
S
Address Hold Time after CE High (Erase)
T
AHC
2.0
-
-
S
Note: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
W27C257
- 8 -
TIMING WAVEFORMS
AC Read Waveform
CE
Outputs
T
High Z
High Z
Valid Output
CE
T
OE
T
ACC
T
OH
T
DF
Address
Address Valid
V
IL
V
IH
V
IH
V
IL
V
IH
V
IL
OE
Erase Waveform
Address
Read
SID
Device
Read
SID
A9 = 12.0V
Others = V
IL
A0 = V
IL
Data
Chip Erase
A9 = 14.0V
Erase Verify
Address
Stable
T
ACC
DA
02
Data All One
14.0V
5.0V
A0= V
IH
5V
Read Verify
Blank Check
Manufacturer
Address
Stable
Address
Stable
Others = V
IL
Others = V
IL
T
ACC
T
AS
T
ARC
T
DS
T
AHC
T
VPS
T
DFP
D
OUT
D
OUT
D
OUT
T
AH
T
ACC
V
IH
V
IL
V
PP
CE
OE
T
CE
T
OE
T
OE
T
OES
T
OEV
T
OE
V
IH
V
IL
V
IH
V
IL
T
PWE
W27C257
Publication Release Date: September 1998
- 9 -
Revision A2
Timing Waveforms, continued
Programming Waveform
Address
Data
12.0V
5.0V
CE
Address Stable
Program
Read
Verify
Address Stable
Address Valid
Verify
Data In Stable
5V
Program
D
OUT
T
AH
D
OUT
D
OUT
T
DH
T
DS
T
VPS
T
ACC
T
DFP
T
AS
V
IH
V
IL
V
IH
V
IL
V
PP
OE
T
OES
T
OEV
T
OE
V
IH
V
IL
T
PWP
W27C257
- 10 -
SMART PROGRAMMING ALGORITHM
Start
Address = First Location
Vcc = 5V
Vpp = 12V
X = 0
Increment X
X = 25?
Verify
One Byte
Last
Address?
Vcc = 5V
Vpp = 5V
Compare
All Bytes to
Original Data
Pass
Device
Increment
Address
No
Fail
Yes
Pass
Fail
Fail
Fail
Device
Verify
One Byte
Program One 100 S Pulse
No
Pass
Yes
Pass
W27C257
Publication Release Date: September 1998
- 11 -
Revision A2
SMART ERASE ALGORITHM
Start
Vcc = 5V
Vpp = 14V
Increment X
Last
Address?
Vcc = 5V
Vpp = 5V
Compare
All Bytes to
FFs (HEX)
Pass
Device
Increment
Address
No
Fail
Fail
Fail
Device
X = 0
A9 = 14V; A0 = V
Chip Erase 100 mS Pulse
Address = First Location
Erase
Verify
X = 20?
No
Yes
Pass
Pass
Yes
IL
W27C257
- 12 -
ORDERING INFORMATION
PART NO.
ACCESS
TIME (nS)
POWER SUPPLY
CURRENT MAX.
(mA)
STANDBY V
CC
CURRENT MAX.
(
A)
PACKAGE
W27C257-10
100
30
100
600 mil DIP
W27C257-12
120
30
100
600 mil DIP
W27C257P-10
100
30
100
32-pin PLCC
W27C257P-12
120
30
100
32-pin PLCC
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
W27C257
Publication Release Date: September 1998
- 13 -
Revision A2
PACKAGE DIMENSIONS
28-pin P-DIP
Seating Plane
1. Dimensions D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.
6. General appearance spec. should be based on
final visual inspection spec.
1.63
1.47
0.064
0.058
Notes:
Symbol
Min. Nom. Max.
Max.
Nom.
Min.
Dimension in Inches
Dimension in mm
A
B
c
D
e
A
L
S
A
A
1
2
E
0.060
1.52
0.210
5.33
0.010
0.150
0.016
0.155
0.018
0.160
0.022
3.81
0.41
0.25
3.94
0.46
4.06
0.56
0.008
0.120
0.670
0.010
0.130
0.014
0.140
0.20
3.05
0.25
3.30
0.36
3.56
0.540
0.550
0.545
13.72
13.97
13.84
17.02
15.24
14.99
15.49
0.600
0.590
0.610
2.29
2.54
2.79
0.090
0.100
0.110
B
1
1
e
E
1
a
1.460
1.470
37.08
37.34
0
15
0.090
2.29
0.650
0.630
16.00
16.51
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
15
0
e
A
2
A
a
c
E
Base Plane
1
A
1
e
L
A
S
1
E
D
1
B
B
28
1
15
14
32-pin PLCC
L
c
1
b
2
A
H
E
E
e
b
D H
D
y
A
A
1
Seating Plane
E
G
G
D
1
13
14
20
29
32
4
5
21
30
Notes:
Symbol
Min.
Nom.
Max.
Max.
Nom.
Min.
Dimension in Inches
Dimension in mm
A
b
c
D
e
H
E
L
y
A
A
1
2
E
b
1
G
D
3.56
0.50
2.80
2.67
2.93
0.71
0.66
0.81
0.41
0.46
0.56
0.20
0.25
0.35
13.89
13.97
14.05
11.35
11.43
11.51
1.27
H
D
G
E
12.45
12.95
13.46
9.91
10.41
10.92
14.86
14.99
15.11
12.32
12.45
12.57
1.91
2.29
0.004
0.095
0.090
0.075
0.495
0.490
0.485
0.595
0.590
0.585
0.430
0.410
0.390
0.530
0.510
0.490
0.050
0.453
0.450
0.447
0.553
0.550
0.547
0.014
0.010
0.008
0.022
0.018
0.016
0.032
0.026
0.028
0.115
0.105
0.110
0.020
0.140
1. Dimension D & E do not include interlead flash.
2. Dimension b does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches.
4. General appearance spec. should be based on final visual
inspection spec.
1.12
1.42
0.044
0.056
0
10
10
0
0.10
2.41
W27C257
- 14 -
VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
Mar. 1998
Initial Issued
A2
Sep. 1998
6
Correct Imput High Voltage (V
IH
) from 2.0 (min) to 2.2 (max)
4 , 6, 7
Correct Vcc from 5.0
10% to 5.0
5%
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change without notice.
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