W49F020

256K

× 8 CMOS FLASH MEMORY

Publication Release Date: February 21, 2003

- 1 -

Revision A3

1. GENERAL DESCRIPTION

The W49F020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K

× 8 bits. The device

can be programmed and erased in-system with a standard 5V power supply. A 12-volt V

is not

required. The unique cell architecture of the W49F020 results in fast program/erase operations with
extremely low current consumption (compared to other comparable 5-volt flash memory products). The
device can also be programmed and erased using standard EPROM programmers.

2. FEATURES

Single 5-volt operations:

- 5-volt read

- 5-volt erase

- 5-volt program

Fast Program operation:

- Byte-by-Byte programming: 50 µS (max.)

Fast erase operation: 100 mS (typ.)

Fast read access time: 70/90 nS

Endurance: 10K cycles (typ.)

Twenty-year data retention

Hardware data protection

One 8K Byte boot block with lockout protection

Low power consumption

- Active current: 25 mA (typ.)

- Standby current: 20 µA (typ.)

Automatic program and erase timing with

internal

generation

End of program or erase detection

- Toggle bit

- Data polling

Latched address and data

TTL compatible I/O

JEDEC standard byte-wide pinouts

Available packages: 32-pin DIP and 32-pin

TSOP and 32-pin-PLCC

W49F020

- 2 -

3. PIN CONFIGURATIONS

DQ0

DQ1

DQ2

#OE

#CE
DQ7
DQ6

DQ5

DQ4
DQ3

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15

Vss

A10

32-pin

TSOP

A15

A12

A7
A6
A5
A4

#WE

A14

A13

A11

32
31
30
29
28
27
26
25
24

22
2

20
19
18
17

A16

A17

#RESET

1
2

11
12

18
17

DQ0

DQ1

DQ2

Vss

A7
A6

A16

A15
A12

#WE

A14

A13

A8
A9

A11

#OE
A10

#CE
DQ7

DQ6

DQ5

DQ4

DQ3

A17

32-pin

DIP

#RESET

5
6

DQ0

A14

A13

A11

#OE
A10

#CE
DQ7

32-pin

PLCC

4. BLOCK DIAGRAM

CONTROL

OUTPUT

BUFFER

DECODER

#CE

#OE

#WE

A17

DQ0

VDD

VSS

DQ7

02000

01FFF

00000

MAIM MEMORY

248K BYTES

BOOT BLOCK

8K BYTES

3FFFF

#RESET

5. PIN DESCRIPTION

SYMBOL

PIN NAME

- A17

Address Inputs

DQ0

- DQ7

Data Inputs/Outputs

#CE

Chip Enable

#OE

Output Enable

#WE Write

Enable

#RESET Reset

Power Supply

Ground

No Connection

W49F020

Publication Release Date: February 21, 2003

- 3 -

Revision A3

6. FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W49F020 is controlled by #CE and #OE, both of which have to be low for the
host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is
de-selected and only standby power will be consumed. #OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either #CE or #OE is high.
Refer to the timing waveforms for further details.

Reset Operation

The #RESET pin provides a hardware method of resetting the device to reading array data. When the
system drives the #RESET pin low for at least a period of t

RSTP

, the device immediately terminates any

operation in progress and ignores all attempts for the duration of the #RESET pulse. The device also
resets the internal state machine to reading array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the #RESET pulse. When #RESET is held at V

, the device enters

the TTL standby mode; if #RESET is held at Vss, the device enters the CMOS standby mode.
The #RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

Boot Block Operation

There is an 8K-byte boot block in this device, which can be used to store boot code. The boot block
locates in the first 8K bytes of the memory with the address range from 0000(hex) to 1FFF(hex). For the
specific code, please see Command Codes for Boot Block Lockout Enable.
When the boot block is enabled, data for the designated block cannot be erased or programmed
(programming lockout); other memory locations can be changed by the regular programming method.
When the boot block programming lockout feature is activated, the chip erase function cannot erase the
boot block any longer.
In order to detect whether the boot block feature is set on the 8K-bytes block or not, users can perform
software command sequence to check it. First, enter the product identification mode (see Command
Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address
"0002 hex". If the output data is "1," the boot block programming lockout feature is activated; if the
output data is "0," the lockout feature is inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed
in a fast 100 mS (typical). The host system is not required to provide any control or timing during this
operation. If the boot block programming lockout is activated, only the data in the main memory blocks
will be erased to FF(hex), and the data in the boot block will not be erased (remains same as before the
chip erase operation). The entire memory array will be erased to FF hex by the chip erase operation if
the boot block programming lockout feature is not activated. Once the boot block lockout feature is
activated, the chip erase function erase the main memory block but not the boot block. The device will

W49F020

- 4 -

automatically return to normal read mode after the erase operation completed. Data polling and/or
Toggle Bits can be used to detect end of erase cycle.

Program Operation

The W49F020 is programmed on a byte-by-byte basis. Program operation can only change logical data
"1" to logical data "0." The erase operation (changed entire data in main memory blocks and/or boot
block from "0" to "1") is needed before programming.
The program operation is initiated by a 4-word command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the
byte-program command is entered. The internal program timer will automatically time-out (50

µS max. -

) when completing programming and return to normal read mode. Data polling and/or Toggle Bits

can be used to detect end of program cycle.

Hardware Data Protection

The integrity of the data stored in the W49F020 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse with less than 15 nS in duration will not initiate a write cycle.
(2) V

Power Up/Down Detection: The programming and read operation are inhibited when V

less than 2.5V typical.

(3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) V

power-on delay: When V

has reached its sense level, the device will automatically time-out

5 mS before any write (erase/program) operation.

Data Polling (DQ

)- Write Status Detection

The W49F020 features a data polling function which used to indicate the end of a program or erase
cycle. When the W49F020 is in the internal program or erase cycle, any attemption to read DQ

of the

last word loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ

will show the true data. Note that DQ

will show logical "0" during the erase cycle, and

become logical "1" or true data when the erase cycle has been completed.

Toggle Bit (DQ

)- Write Status Detection

In addition to data polling, the W49F020 provides another method for determining the end of a program
cycle. During the internal program or erase cycle, any consecutive attempts to read DQ

will produce

alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's
will stop. The device is then ready for the next operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In software
access mode, a three-word (or JEDEC 3-word) command sequence can be used to access the product
ID. A read from address 0000H outputs the manufacturer code DA(hex); and a read from address
0001H outputs the device code 8C(hex) for W49F020. The product ID operation can be terminated by a
three-word command sequence or an alternated one-word command sequence (see Command
Definition table).

W49F020

Publication Release Date: February 21, 2003

- 5 -

Revision A3

In the hardware access mode, access to the product ID will be activated by forcing #CE and #OE low,
#WE high, and raising A9 to 12 volts.

Table of Operating Modes

Operating Mode Selection

= 12V

± 5%)

PINS

MODE

#CE #OE #WE #RESET

ADDRESS DQ0-DQ7

Read V

Dout

Write V

Din

Standby V

X X V

High

X V

X X

High

Z/D

OUT

Write Inhibit

X X V

High

Z/D

OUT

Output Disable

X V

High

Reset X

High

A0 = V

; A1

- A17 = V

;

A9 = V

Manufacturer Code
DA (Hex)

Product ID

A0 = V

; A1

- A17 = V

;

A9 = V

Device Code 8C
(Hex)

Table of Command Definition

COMMAND

NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE

DESCRIPTION

Cycles Addr. Data

Addr. Data

Addr. Data Addr. Data

OUT

Chip Erase

5555 AA

2AAA 55

5555 80

5555 AA

2AAA 55

5555 10

Byte Program

5555 AA

2AAA 55

5555 A0

Boot Block Lockout

5555 AA

2AAA 55

5555 80

5555 AA

2AAA 55

5555 40

Product ID Entry

5555 AA

2AAA 55

5555 90

Product ID Exit

(1)

5555 AA

2AAA 55

5555 F0

Product ID Exit

(1)

XXXX F0

Notes:
1. Address Format: A14

- A0 (Hex); Data Format: DQ7 - DQ0 (Hex)

2. Either one of the two Product ID Exit commands can be used.

W49F020

Publication Release Date: February 21, 2003

- 9 -

Revision A3

Software Product Identification and Boot Block Lockout Detection Acquisition Flow

Product

Identification
Entry (1)

Load data 55

address 2AAA

Load data 90

address 5555

Pause 10 S

Product

Identification

and Boot Block

Lockout Detection

Mode (3)

Read address = 00000

data = DA

Read address = 00001

data = 8C

Read address = 00002

data = FF/FE

(4)

Product

Identification Exit (6)

Load data 55

address 2AAA

Load data F0

address 5555

Normal Mode

(5)

(2)

Load data AA

address 5555

Load data AA

address 5555

Pause 10 S

Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ15-DQ8 (Don't Care), DQ7

- DQ0 (Hex); Address Format: A14 - A0 (Hex)

(2) A1

- A15 = V

; manufacture code is read for A0 = V

; device code is read for A0 = V

(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is
inactivated and the block can be programmed.
(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.

W49F020

- 11 -

7. ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING

UNIT

Power Supply Voltage to V

Potential

-0.5 to +7.0

Operating Temperature

0 to +70

°C

Storage Temperature

-65 to +150

°C

D.C. Voltage on Any Pin to Ground Potential except #OE

-0.5 to V

+1.0

Transient Voltage (<20 nS) on Any Pin to Ground Potential

-1.0 to V

+1.0

Voltage on #OE Pin to Ground Potential

-0.5 to 12.5

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

DC Operating Characteristics

= 5.0V

, V

= 0V, T

= 0 to 70

LIMITS

PARAMETER SYM.

TEST

CONDITIONS

MIN. TYP. MAX.

UNIT

Power Supply
Current

#CE = #OE = V

, #WE = V

all DQs open
Address inputs = V

, at f = 5 MHz

- 25 50 mA

Standby V

Current (TTL input)

#CE = V

, all DQs open

Other inputs = V

- 2 3 mA

Standby V

Current

(CMOS input)

#CE = V

-0.3V, all DQs open

Other inputs = V

-0.3V/ V

- 20 100

µA

Input Leakage
Current

= V

to V

- - 10

µA

Output Leakage
Current

OUT

= V

to V

- - 10

µA

Input Low Voltage

- -0.3

0.8

Input High Voltage

- 2.0

+0.5

Output Low Voltage

= 2.1 mA

0.45

Output High Voltage V

= -0.4 mA

2.4

W49F020

- 12 -

Power-up Timing

PARAMETER SYMBOL

TYPICAL

UNIT

Power-up to Read Operation

. READ

100

µS

Power-up to Write Operation

. WRITE

Capacitance

= 5.0V, T

= 25

C, f = 1 MHz)

PARAMETER SYMBOL

CONDITIONS MAX.

UNIT

I/O Pin Capacitance

I/O

= 0V

Input Capacitance

= 0V

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels

0V to 3.0V

Input Rise/Fall Time

< 5 nS

Input/Output Timing Level

1.5V/1.5V

Output Load

1 TTL Gate and C

= 100 pF for 90 nS

= 30 pF for 70 nS

AC Test Load and Waveform

+5V

1.8K

1.3K

OUT

30 pF for 70nS

(Including Jig and

Scope)

Input

Test Point

1.5V

Output

100 pF for 90nS

W49F020

Publication Release Date: February 21, 2003

- 13 -

Revision A3

Read Cycle Timing Parameters

= 5.0V

, V

= 0V, T

= 0 to 70

W49F020-70 W49F020-90

PARAMETER

SYM.

MIN. MAX. MIN. MAX.

UNIT

Read Cycle Time

70 - 90 - nS

Chip Enable Access Time

- 70 - 90

Address Access Time

- 70 - 90

Output Enable Access Time

- 35 - 40

#CE

Low to Active Output

CLZ

0 - 0 -

#OE

Low to Active Output

OLZ

0 - 0 -

#CE

High to High-Z Output

CHZ

- 25 - 25

#OE

High to High-Z Output

OHZ

- 25 - 25

Output Hold from Address Change

0 - 0 -

Write Cycle Timing Parameters

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

Address Setup Time

0 - -

Address Hold Time

50 - - nS

#WE

and

#CE

Setup Time

0 - -

#WE

and

#CE

Hold Time

0 - -

#OE

High Setup Time

OES

0 - -

#OE

High Hold Time

OEH

0 - -

#CE

Pulse Width

100 - - nS

#WE

Pulse Width

100 - - nS

#WE

High Width

WPH

100 - - nS

Data Setup Time

50 - - nS

Data Hold Time

0 - -

Byte programming Time

- 10 50

µS

Erase Cycle Time

- 0.1 1 S

Note: All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is V

and (b) low level signal's reference level is V

W49F020

- 20 -

10. ORDERING INFORMATION

PART NO.

ACCESS

TIME

(nS)

POWER

SUPPLY

CURRENT

MAX. (mA)

STANDBY V

CURRENT

MAX.

(

µA)

PACKAGE CYCLE

W49F020-90B

100 (CMOS)

32-pin DIP

10K

W49F020T-70B 70 50

100

(CMOS)

32-pin TSOP (8 mm

× 20 mm)

10K

W49F020T-90B 90 50

100

(CMOS)

32-pin TSOP (8 mm

× 20 mm)

10K

W49F020P-70B

100 (CMOS)

32-pin PLCC

10K

W49F020P-90B

100 (CMOS)

32-pin PLCC

10K

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
3. The part number shown in the Ordering Information table is only for Bottom Boot Block part, which is in the lower address range.

For the requirement of the higher address range boot block, the Top Boot Block, please contact Winbond FAE for details.

11. HOW TO READ THE TOP MARKING

Example: The top marking of 32-pin PLCC W49F020P-90B

line: winbond logo

line: the part number: W49F020P-90B

line: the lot number

line: the tracking code: 149 O B SA

149: Packages made in '01, week 49
O: Assembly house ID: A means ASE, O means OSE, ...etc.
B: IC revision; A means version A, B means version B, ...etc.
SA: Process code

W49F020P-90B

2138977A-A12

149OBSA

W49F020

Publication Release Date: February 21, 2003

- 21 -

Revision A3

12. PACKAGE DIMENSIONS

32-pin P-DIP

1.Dimensions D Max. & S include mold flash or

tie bar burrs.

2.Dimension E1 does not include interlead flash.

3.Dimensions D & E1 include mold mismatch and

are determined at the mold parting line.

6.General appearance spec. should be based on

final visual inspection spec.

1.37

1.22

0.054

0.048

Notes:

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in inches

Dimension in mm

c
D

A
A

0.050

1.27

0.210

5.33

0.010

0.150

0.016

0.155

0.018

0.160

0.022

3.81

0.41

0.25

3.94

0.46

4.06

0.56

0.008

0.120

0.670

0.010

0.130

0.014

0.140

0.20

3.05

0.25

3.30

0.36

3.56

0.555

0.550

0.545

14.10

13.97

13.84

17.02

15.24

14.99

15.49

0.600

0.590

0.610

2.29

2.54

2.79

0.090

0.100

0.110

1.650

1.660

41.91

42.16

0.085

2.16

0.650

0.630

16.00

16.51

protrusion/intrusion.

4.Dimension B1 does not include dambar

5.Controlling dimension: Inches

Seating Plane

Base Plane

32-pin PLCC

Notes:

D H

Seating Plane

1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches

4. General appearance spec. should be based on final

visual inspection sepc.

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in Inches

Dimension in mm

b
c
D

A
A

3.56

0.50

2.80

2.67

2.93

0.71

0.66

0.81

0.41

0.46

0.56

0.20

0.25

0.35

13.89

13.97

14.05

11.35

11.43

11.51

1.27

12.45

12.9

13.46

9.91

10.41

10.92

14.86

14.99

15.11

12.32

12.45

12.57

1.91

2.29

0.004

0.095

0.090

0.075

0.495

0.49

0.485

0.595

0.590

0.585

0.430

0.410

0.390

0.530

0.51

0.490

0.050

0.453

0.450

0.447

0.553

0.550

0.547

0.014

0.010

0.008

0.022

0.018

0.016

0.032

0.026

0.028

0.115

0.105

0.110

0.020

0.140

1.12

1.42

0.044

0.056

0.10

2.41

W49F020

- 22 -

Package Dimensions, continued

32-pin TSOP

0.10(0.004)

Min.

Nom.

Max.

Min.

Nom.

Max.

Symbol

Note:

Controlling dimension: Millimeters

Dimension in Inches

0.047

0.006

0.041

0.039

0.037

0.007

0.008

0.009

0.005

0.006

0.007

0.720

0.724

0.728

0.311

0.315

0.319

0.780

0.787

0.795

0.020

0.016

0.020

0.024

0.031

0.000

0.004

0.002

1.20

0.05

0.15

1.05

1.00

0.95

0.17

0.12

18.30

7.90

19.80

0.40

0.00

0.20

0.23

0.15

0.17

18.40

18.50

8.00

8.10

20.00

20.20

0.50

0.60

0.80

0.10

Dimension in mm

W49F020

Publication Release Date: February 21, 2003

- 23 -

Revision A3

13. VERSION HISTORY

VERSION DATE

PAGE

DESCRIPTION

Oct. 1999

Initial Issued

Dec. 18, 2002

1, 21

Delete 1K endurance

Change W49F020Q 70/90 to W49F020T-70/90

Modify the description of V

Power Up/Down

Detection in Hardware Data Protection

6-10

Delete old flow chart and add embedded algorithm

Correct Part. No for ordering information

Delete Part. No of W49F020-70B for ordering

information

Add HOW TO READ THE TOP MARKING

2, 3, 14, 19

Add in #RESET function

Feb. 21, 2003

Correct Embedded Erase Algorithm
(Delete Main-memory Erase Command Sequence)

Correct VA(Valid Address) definition in Embedded
#Data Polling Algorithm

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

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