W49V002FA

256K

8 CMOS FLASH MEMORY

WITH FWH INTERFACE

Publication Release Date: February 19, 2002

- 1 - Revision A2

GENERAL DESCRIPTION

The W49V002FA is a 2-megabit, 3.3-volt only CMOS flash memory organized as 256K

8 bits. The

device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt V

not required. The unique cell architecture of the W49V002FA results in fast program/erase operations
with extremely low current consumption. This device can operate at two modes, Programmer bus
interface mode and FWH bus interface mode. As in the Programmer interface mode, it acts like the
traditional flash but with a multiplexed address inputs. But in the FWH interface mode, this device
complies with the Intel FWH specification. The device can also be programmed and erased using
standard EPROM programmers.

FEATURES

Single 3.3-volt operations:

3.3-volt Read

3.3-volt Erase

3.3-volt Program

Fast program operation:

Byte-by-byte programming: 50

S (typ.)

Fast erase operation: 150 mS (typ.)

Fast read access time: Tkq 11 nS

Endurance: 10K cycles (typ.)

Twenty-year data retention

Hardware data protection

#TBL & #WP serve as hardware protection

One 16K bytes Boot Block with lockout

protection

Two 8K bytes Parameter Blocks

Four main memory blocks (with 32K bytes, 64K

bytes, 64K bytes, 64K bytes each)

Low power consumption

Active current: 40 mA (typ. for FWH)

Automatic program and erase timing with

internal V

generation

End of program or erase detection

Toggle bit

Data polling

Latched address and data

TTL compatible I/O

Available packages: 32L PLCC, 32L STSOP

W49V002FA

- 2 -

PIN CONFIGURATIONS

D
Q

F
W
H
1

N
D

D
Q

R
S
V

R
E
S
E
T

V
D
D

C
L
K
v

F
G
P
I
3
v

32L

PLCC

0
^

F
G
P
I
4

DQ0(FWH0)

A7(FGPI1)

A6(FGPI0)

A4(#TBL)

A3(ID3)

A2(ID2)

A1(ID1)

A0(ID0)

A5(#WP)

VDD

DQ7(RSV)

#WE(FWH4)

#OE(#INIT)

GND

F
G
P
I
2
v

D
Q

F
W
H
2

D
Q

F
W
H
3
v

D
Q

R
S
V

D
Q

R
S
V

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25

32L

TSOP

24
23
22
21

#WE(FWH4)

DQ4(RSV)
DQ3(FWH3)

DQ7(RSV)
DQ6(RSV)

#OE(#INIT)

DQ5(RSV)

20
19
18
17

GND

A3(ID3)

R/#C(CLK)

GND

A10(FGPI4)

A4(#TBL)

A9(FGPI3)
A8(FGPI2)

#RESET

A7(FGPI1)
A6(FGPI0)

A5(#WP)

A2(ID2)

A1(ID1)

A0(ID0)

DQ2(FWH2)

DQ1(FWH1)
DQ0(FWH0)

BLOCK DIAGRAM

Program-
mer
Interface

3FFFF

00000

BOOT BLOCK
16K BYTES

MAIN MEMORY
BLOCK1
32K BYTES

20000
1FFFF

3C000
3BFFF

10000
0FFFF

PARAMETER
BLOCK1
8K BYTES

PARAMETER
BLOCK2
8K BYTES

3A000
39FFF

38000
37FFF

#RESET

Interface

CLK

FWH4

FWH[3:0]

A[10:0]

DQ[7:0]

#OE

#WE

R/#C

MAIN MEMORY
BLOCK2
64K BYTES

MAIN MEMORY
BLOCK3
64K BYTES

30000
2FFFF

MAIN MEMORY
BLOCK4
64K BYTES

#INIT

#TBL

#WP

PIN DESCRIPTION

SYM.

INTERFACE

PIN NAME

PGM FWH

Interface Mode Selection

#RESET

Reset

#INIT

Initialize

#TBL

Top Boot Block Lock

#WP

Write Protect

CLK

CLK Input

FGPI[4:0]

General Purpose Inputs

ID[3:0]

Identification Inputs They
Are Internal Pull Down to
V

FWH[3:0]

Address/Data Inputs

FWH4

FWH Cycle Initial

R/#C

Row/Column Select

A[10:0]

Address Inputs

DQ[7:0]

Data Inputs/Outputs

#OE

Output Enable

#WE

Write Enable

Power Supply

GND

Ground

RSV

Reserved Pins

No Connection

W49V002FA

Publication Release Date: February 19, 2002

- 3 - Revision A2

FUNCTIONAL DESCRIPTION

Interface Mode Selection And Description

This device can be operated in two interface modes, one is Programmer interface mode, the other is
FWH interface mode. The IC pin of the device provides the control between these two interface
modes. These interface modes need to be configured before power up or return from #RESET

When

IC pin is set to high state, the device will be in the Programmer mode; while the IC pin is set to low
state (or leaved no connection), it will be in the FWH mode. In Programmer mode, this device just
behaves like traditional flash parts with 8 data lines. But the row and column address inputs are
multiplexed, which go through address inputs A[10:0]. For FWH mode, It complies with the FWH
Interface Specification. Through the FWH[3:0] to communicate with the system chipset .

Read (Write) Mode

In Programmer interface mode, the read (write) operation of the W49V002FA is controlled by #OE
(#WE). The #OE(#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE
is the output control and is used to gate data from the output pins. The data bus is in high impedance
state when #OE is high. As for in the FWH interface mode, the read or write is determined by the "bit 0
& bit 1 of START CYCLE ". Refer to the FWH cycle definition for further details.

Reset Operation

The #RESET input pin can be used in some application. When #RESET pin is at high state, the device
is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will
be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to
read or standby mode, it depends on the control signals.

Chip Erase Operation

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed within fast 150 mS (typical). The host system is not required to provide any control or timing
during this operation. If the boot block programming lockout is activated, only the data in the other
memory blocks will be erased to FF(hex) while the data in the boot block will not be erased (remains
as the same state before the chip erase operation). The entire memory array will be erased to FF(hex)
by the chip erase operation if the boot block programming lockout feature is not activated. The device
will automatically return to normal read mode after the erase operation completed. Data polling and/or
Toggle Bits can be used to detect end of erase cycle.

Sector Erase Operation

The seven sectors, one boot block and two parameter memory and four main blocks, can be erased
individually by initiating a six-byte command sequence. Sector address is latched on the falling #WE
edge of the sixth cycle, while the 30(hex) data input command is latched at the rising edge of #WE.
After the command loading cycle, the device enters the internal sector erase mode, which is
automatically timed and will be completed within fast 150 mS (typical). The host system is not required
to provide any control or timing during this operation. The device will automatically return to normal
read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect
end of erase cycle.

W49V002FA

- 4 -

Program Operation

The W49V002FA is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or
boot block from "0" to "1", is needed before programming.

The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the byte-
program command is entered. The internal program timer will automatically time-out (100

S max. -

) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be

used to detect end of program cycle.

Boot Block Operation and Hardware Protection at Initial- #TBL & #WP

There are two alternatives to set the boot block. One is software command sequences method; the
other is hardware method. 16K-byte in the top location of this device can be locked as boot block,
which can be used to store boot codes. It is located in the last 16K bytes of the memory with the
address range from 3C000(hex) to 3FFFF(hex).

Please see Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is
set, the data for the designated block cannot be erased or programmed (programming lockout), other
memory locations can be changed by the regular programming method.

Besides the software method, there is a hardware method to protect the top boot block and other
sectors. Before program/erase to this device, set the #TBL pin to low state and then the top boot block
will not be programmed/erased. When enabling hardware top boot block, #TBL being low state, it will
override the software method setting. That is, if #TBL is at low state, then top boot block cannot be
programmed/erased no matter how the software boot block lock setting.

Another pin, #WP, will protect the whole chip if this pin is set to low state before program/erase. The
enable of this pin will override the #TBL setting. That is, the top boot block cannot be
programmed/erased if this pin is set to low no matter how the #TBL or software boot block lock setting.

Hardware Data Protection

The integrity of the data stored in the W49V002FA is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) V

Power Up/Down Detection: The programming and read operation are inhibited when V

less than 1.5V typical.

(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents

inadvertent writes during power-up or power-down periods.

(4) V

power-on delay: When V

has reached its sense level, the device will automatically time-out 5

mS before any write (erase/program) operation.

Data Polling (DQ

)- Write Status Detection

The W49V002FA includes a data polling feature to indicate the end of a program or erase cycle.
When the W49V002FA is in the internal program or erase cycle, any attempts to read DQ

of the last

byte loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ

will show the true data. Note that DQ

will show logical "0" during the erase cycle, and

when erase cycle has been completed it becomes logical "1" or true data.

W49V002FA

Publication Release Date: February 19, 2002

- 5 - Revision A2

Toggle Bit (DQ

)- Write Status Detection

In addition to data polling, the W49V002FA provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ

will

produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.

General Purpose Inputs Register

This register reads the FGPI[4:0] pins on the W49V002FA.This is a pass-through register which can
read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value.

BIT

FUNCTION

5 Reserved

Read FGPI4 pin status

Read FGPI3 pin status

Read FGPI2 pin status

Read FGPI1 pin status

Read FGPI0 pin status

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software operation. In the software access
mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID for
programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex).
A read from address 0001(hex) outputs the device code, 32(hex)." The product ID operation can be
terminated by a three-byte command sequence or an alternate one-byte command sequence (see
Command Definition table).

As for FWH interface mode, a read from FFBC, 0000(hex) can output the manufacturer code,
DA(hex). A read from FFBC, 0001(hex) can output the device code 32(hex).

TABLE OF OPERATING MODES

Operating Mode Selection - Programmer Mode

= 12V

)

MODE

PINS

#OE

#WE #RESET

ADDRESS

DQ.

Read

AIN

Dout

Write

AIN

Din

Standby

High Z

Write Inhibit

High Z/DOUT

Output Disable

High Z

W49V002FA

- 6 -

Operating Mode Selection - FWH Mode

Operation modes in FWH interface mode are determined by "START Cycle" when it is selected. When
it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle
Definition".

TABLE OF COMMAND DEFINITION

COMMAND

NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE

DESCRIPTION

Cycles Addr. Data

Addr. Data

Addr. Data Addr. Data Addr. Data Addr. Data

Read

OUT

Chip Erase

5555 AA

2AAA 55

5555 80

5555 AA

2AAA 55

5555 10

Sector Erase

5555 AA

2AAA 55

5555 80

5555 AA

2AAA 55

SA 30

Byte Program

5555 AA

2AAA 55

5555 A0

Boot Block Lockout

5555 AA

2AAA 55

5555 80

5555 AA

2AAA 55

5555 40

Product ID Entry

5555 AA

2AAA 55

5555 90

Product ID Exit

(1)

5555 AA

2AAA 55

5555 F0

Product ID Exit

(1)

XXXX F0

Notes:

1. The cycle means the write command cycle not the FWH clock cycle.
2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address

A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]

3. Address Format: A14

A0 (Hex); Data Format: DQ7-DQ0 (Hex)

4. Either one of the two Product ID Exit commands can be used.
5. SA: Sector Address

SA = 3C000h to 3FFFFh for Boot Block
SA = 3A000h to 3BFFFh for Parameter Block1
SA = 38000h to 39FFFh for Parameter Block2
SA = 30000h to 37FFFh for Main Memory Block1
SA = 2XXXXh for Main Memory Block2
SA = 1XXXXh for Main Memory Block3
SA = 0XXXXh for Main Memory Block4

W49V002FA

Publication Release Date: February 19, 2002

- 7 - Revision A2

FWH CYCLE DEFINITION

FIELD

NO. OF

CLOCKS

DESCRIPTION

START

"1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH
Memory Write cycle.

IDSEL

This one clock field indicates which FWH component is being selected.

MSIZE

Memory Size. There is always show "0000b" for single byte access.

TAR

Turned Around Time

ADDR

Address Phase for Memory Cycle. FWH supports the 28 bits address
protocol. The addresses transfer most significant nibble first and least
significant nibble last. (i.e. Address[27:24] on FWH[3:0] first , and
Address[3:0] on FWH[3:0] last.)

SYNC

Synchronous to add wait state. "0000b" means Ready, "0101b" means
Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"
means error, and other values are reserved.

DATA

Data Phase for Memory Cycle. The data transfer least significant nibble first
and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first , then
DQ[7:4] on FWH[3:0] last.)

W49V002FA

Publication Release Date: February 19, 2002

- 11 - Revision A2

Software Product Identification and Boot Block Lockout Detection Acquisition
Flow

Product

Identification

Entry (1)

Load data 55

address 2AAA

Load data 90

address 5555

Pause 10 S

Product

Identification
and Boot Block
Lockout Detection
Mode (3)

Read address = 00000

data = DA

Read address = 00001

data = 32 (Hex)

Read address = 00002

DQ0 of data outputs = 1/0

(4)

Product

Identification Exit(6)

Load data 55

address 2AAA

Load data F0

address 5555

Normal Mode

(5)

(2)

Load data AA

address 5555

Load data AA

address 5555

Pause 10 S

Notes for software product identification/boot block lockout detection:

(1) Data Format: DQ7

DQ0 (Hex); Address Format: A14

A0 (Hex)

(2) A1

A17 = V

; manufacture code is read for A0 = V

; device code is read for A0 = V

(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the DQ0 of output data "0," the

lockout feature is inactivated and the block can be programmed.

(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout

detection.

W49V002FA

Publication Release Date: February 19, 2002

- 13 - Revision A2

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

UNIT

Power Supply Voltage to V

Potential

-0.5 to +4.1

Operating Temperature

0 to +70

Storage Temperature

-65 to +150

D.C. Voltage on Any Pin to Ground Potential

-0.5 to V

+0.5

Transient Voltage (<20 nS) on Any Pin to Ground Potential

-1.0 to V

+0.5

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

Programmer interface Mode DC Operating Characteristics

= 3.3V

5%, V

GND

= 0V, T

= 0 to 70

PARAMETER

SYM.

TEST CONDITIONS

LIMITS

UNIT

MIN. TYP. MAX.

Power Supply
Current

In Read or Write mode, all DQs open

Address inputs = 3.0V/0V, at f = 3 MHz

Input Leakage
Current

= GND to V

Output Leakage
Current

OUT

= GND to V

Input Low Voltage

-0.3

0.8

Input High Voltage

2.0 -

+0.5

Output Low Voltage V

= 2.1 mA

0.45

Output High Voltage V

= -0.1mA

2.4

W49V002FA

- 14 -

FWH interface Mode DC Operating Characteristics

= 3.3V

5 %, V

GND

= 0V, T

= 0 to 70

PARAMETER

SYM.

TEST CONDITIONS

LIMITS

UNIT

MIN. TYP.

MAX.

Power Supply
Current

All I

out

= 0A, CLK = 33 MHz,

in FWH mode operation.

Standby Current

1 FWH4 = 0.9 V

, CLK = 33 MHz,

all inputs = 0.9 V

/ 0.1 V

DD,

internal operation

100

Standby Current

2 FWH4

= 0.1 V

, CLK = 33 MHz,

all inputs = 0.9 V

/ 0.1 V

DD,

no internal operation

Input Low Voltage

-0.5

0.3 V

Input High Voltage

0.5 V

+0.5

Input Low Voltage for
#INIT

ILI

-0.5V

0.2 V

Input High Voltage
for #INIT

IHI

1.35V

+0.5

Output Low Voltage V

= 1.5 mA

0.1 V

Output High Voltage V

= -0.5 mA

0.9 V

Power-up Timing

PARAMETER

SYMBOL

TYPICAL

UNIT

Power-up to Read Operation

. READ

100

Power-up to Write Operation

. WRITE

CAPACITANCE

= 3.3V, T

= 25

C, f = 1 MHz)

PARAMETER

SYMBOL

CONDITIONS

MAX.

UNIT

I/O Pin Capacitance

I/O

= 0V

Input Capacitance

= 0V

W49V002FA

- 16 -

Programmer Interface Mode AC Characteristics, continued

AC Characteristics

Read Cycle Timing Parameters

= 3.3V

5%, V

GND

= 0V, T

= 0 to 70

PARAMETER

SYMBOL

W49V002FA

UNIT

MIN.

MAX.

Read Cycle Time

300

Row/Column Address Set Up Time

Row/Column Address Hold Time

Address Access Time

200

Output Enable Access Time

100

#OE Low to Active Output

OLZ

#OE High to High-Z Output

OHZ

Output Hold from Address Change

Write Cycle Timing Parameters

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Reset Time

RST

Address Setup Time

Address Hold Time

R/#C to Write Enable High Time

CWH

#WE Pulse Width

100

#WE High Width

WPH

100

Data Setup Time

Data Hold Time

#OE Hold Time

OEH

Byte programming Time

100

Erase Cycle Time

0.15

0.2

Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.

Ref. to the AC testing condition.

Data Polling and Toggle Bit Timing Parameters

PARAMETER

SYMBOL

W49V002FA

UNIT

MIN.

MAX.

#OE to Data Polling Output Delay

OEP

#OE to Toggle Bit Output Delay

OET

W49V002FA

- 18 -

Timing Waveforms for Programmer Interface Mode, continued

Program Cycle Timing Diagram

A[10:0]

Byte 0

Byte 1

Byte 2

Internal Write Start

DQ[7:0]

Byte Program Cycle

WPH

5555

2AAA

Programmed Address

Data-In

Byte 3

Note: The internal address A[17:0] are converted from external Column/Row address.

Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].

(Internal A[17:0])

#OE

#WE

#DATA Polling Timing Diagram

A[10:0]

DQ7

OEP

BP or

(Internal A[17:0])

#OE

#WE

W49V002FA

Publication Release Date: February 19, 2002

- 19 - Revision A2

Timing Waveforms for Programmer Interface Mode, continued

Toggle Bit Timing Diagram

A[10:0]

DQ6

OET

BP or

#OE

#WE

Boot Block Lockout Enable Timing Diagram

SB2

SB1

SB0

DQ[7:0]

SB3

SB4

SB5

WPH

Note: The internal address A[17:0] are converted from external Column/Row address.

Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].

(Internal A[17:0])

Six-byte code for 3.3V-only software chip erase

5555

2AAA

5555

2AAA

5555

A[10:0]

#OE

#WE

W49V002FA

- 20 -

Timing Waveforms for Programmer Interface Mode, continued

Chip Erase Timing Diagram

DQ[7:0]

SB2

SB1

SB0

SB3

SB4

SB5

Internal Erasure Starts

WPH

Note: The internal address A[17:0] are converted from external Column/Row address.

Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].

(Internal A[17:0])

Six-byte code for 3.3V-only software chip erase

5555

2AAA

5555

2AAA

5555

A[10:0]

#OE

#WE

Sector Erase Timing Diagram

SB2

SB1

SB0

A[10:0]

DQ[7:0]

SB3

SB4

SB5

Internal Erase starts

Six-byte code for 3.3V-only software

sector erase

WPH

5555

2AAA

5555

2AAA

SA = Sector Address, Please ref. to the "Table of Command Definition"

Note: The internal address A[17:0] are converted from external Column/Row address.

Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].

(Internal A[17:0])

#OE

#WE

W49V002FA

Publication Release Date: February 19, 2002

- 21 - Revision A2

FWH INTERFACE MODE AC CHARACTERISTICS

AC Test Conditions

PARAMETER

CONDITIONS

Input Pulse Levels

0.6 V

to 0.2 V

Input Rise/Fall Slew Rate

1 V/nS

Input/Output Timing Level

0.4 V

/ 0.4 V

Output Load

1 TTL Gate and C

= 10 pF

AC Test Load and Waveform

OUT

10 pF

Input

Test Point

Output

0.2V

0.6V

0.4V

OUT

10 pF

Test when output from low to high

Test when output from high to low

Read/Write Cycle Timing Parameters

= 3.3V

5%, V

GND

= 0V, T

= 0 to 70

PARAMETER

SYMBOL

W49V002FA

UNIT

MIN.

MAX.

Clock Cycle Time

CYC

Input Set Up Time

Input Hold Time

Clock to Data Valid

Reset Timing Parameters

PARAMETER

SYM.

MIN.

TYP.

MAX.

UNIT

stable to Reset Active

PRST

Clock Stable to Reset Active

KRST

100

Reset Pulse Width

RSTP

100

Reset Active to Output Float

RSTF

Reset Inactive to Input Active

RST

Note: All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.

Ref. to the AC testing condition.

W49V002FA

- 22 -

TIMING WAVEFORMS FOR FWH INTERFACE MODE

Read Cycle Timing Diagram

CYC

FWH4

#RESET

FWH[3:0]

Start
FWH
Read

IDSEL

CLK

TAR

Next Start

1 Clock

2 Clocks

1 Clock

A[15:12]

Address

Sync

TAR

1111b

Tri-State

0000b

A[11:8]

A[7:4]

0000b]

Data out 2 Clocks

D[7:4]

Data

D[3:0]

0000b

Load Address in 7 Clocks

A[3:0]

M Size

XXXXb

XA[22]XXb XXA[17:16]

1 Clock

0000b

1101b

Note: When A22 = high, the host will read the BIOS code from the FWH device.

While A22 = low, the host will read the GPI (Add = FFBC0100) or
Product ID (Add = FFBC0000/FFBC0001) from the FWH device

Write Cycle Timing Diagram

TCYC

FWH4

#RESET

FWH[3:0]

Start
FWH
Write

IDSEL

CLK

TAR

Next Start

1 Clock

2 Clocks

1 Clock

A[15:12]

Load Data in 2 Clocks

D[7:4]

Address

Sync

TAR

Data

1111b

Tri-State

0000b

THD

TSU

A[11:8]

A[7:4]

0000b

D[3:0]

0000b

Load Address in 7 Clocks

A[3:0]

M Size

XXXXb

XXA[17:16]b

1 Clock

0000b

1110b

W49V002FA

Publication Release Date: February 19, 2002

- 23 - Revision A2

Timing Waveforms for FWH Interface Mode, continued

Program Cycle Timing Diagram

FWH4

#RESET

FWH[3:0 ]

1st Start

IDSEL

Load Address "5555" in 7 Clocks

CLK

1 Clock

2 Clocks

Load Data "AA" in 2 Clocks

1010b

Write the 1st command to the device in FWH mode.

2nd Start

Load Address "2AAA" in 7 Clocks

1 Clock

2 Clocks

Load Data "55"
in 2 Clocks

0101b

Write the 2nd command to the device in FWH mode.

3rd Start

Load Address "5555" in 7 Clocks

1 Clock

2 Clocks

Load Data "A0"
in 2 Clocks

1010b

0000b

Write the 3rd command to the device in FWH mode.

4th Start

Load Ain in 7 Clocks

FWH4

FWH[3:0 ]

CLK

FWH4

FWH[3:0 ]

CLK

FWH4

FWH[3:0 ]

CLK

Sync

Internal

program start

TAR

1 Clock

2 Clocks

A[15:12]

Load Din in 2 Clocks

D[7:4]

Write the 4th command(target location to be programmed) to the device in FWH mode.

A[11:8]

A[7:4]

A[3:0]

D[3:0]

1111b

Tri-State

0000b

Data

Address

Sync

TAR

Data

Sync

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

1111b

Tri-State

0000b

IDSEL

Internal

program start

IDSEL

0000b

X101b

0101b

X010b

1010b

X101b

0101b

M Size

XXXXb

XXA[17:16]b

XXXXb

1 Clock

0000b

1110b

1 Clock

0000b

1110b

1 Clock

0000b

1110b

1 Clock

0000b

1110b

Start next
command

1 Clock

2 Clocks

TAR

1111b

Tri-State

Start next
command

1 Clock

2 Clocks

TAR

1111b

Tri-State

Start next
command

1 Clock

2 Clocks

TAR

1111b

Tri-State

TAR

2 Clocks

1111b Tri-State

#RESET

W49V002FA

- 24 -

Timing Waveforms for FWH Interface Mode, continued

#DATA Polling Timing Diagram

Read the DQ7 to see if the internal write complete or not.

FWH4

FWH[3:0]

Start

Load Address in 7 Clocks

CLK

1 Clock

2 Clocks

XXXXb

An[15:12]

Address

Sync

TAR

1111b

Tri-State

0000b

An[11:8]

An[7:4]

An[3:0]

Data out 2 Clocks

Dn7,xxx

Data

XXXXb

FWH4

FWH[3:0]

Start

Load Address in 7 Clocks

CLK

1 Clock

2 Clocks

Address

Sync

TAR

1111b

Tri-State

0000b

Data out 2 Clocks

Data

When internal write complete, the DQ7 will equal to Dn7.

Dn7,xxx

XXXXb

An[15:12]

An[11:8]

An[7:4]

An[3:0]

FWH4

FWH[3:0]

Start

Load Address "An" in 7 Clocks

CLK

1 Clock

2 Clocks

An[15:12]

Load Data "Dn"
in 2 Clocks

Dn[7:4]

Write the last command(program or erase) to the device in FWH mode.

Address

Sync

TAR

Data

1111b

Tri-State

0000b

An[11:8]

An[7:4]

An[3:0]

Dn[3:0]

IDSEL

0000b

M Size

XXXXb

XXA[17:16]b

XXXXb

XXA[17:16]b

XXXXb

XXA[17:16]b

XXXXb

1 Clock

2 Clocks

TAR

1111b

Tri-State

Next Start

1 Clock

2 Clocks

TAR

1111b

Tri-State

Next Start

1 Clock

2 Clocks

TAR

1111b

Tri-State

Next Start

1 Clock

0000b

1101b

1 Clock

0000b

1101b

1 Clock

0000b

1110b

#RESET

W49V002FA

Publication Release Date: February 19, 2002

- 25 - Revision A2

Timing Waveforms for FWH Interface Mode, continued

Toggle Bit Timing Diagram

Read the DQ6 to see if the internal write complete or not.

FWH4

Start

Load Address in 7 Clocks

CLK

1 Clock

2 Clocks

Address

Sync

TAR

1111b

Tri-State

0000b

Data out 2 Clocks

X,D6,XXb

Data

XXXXb

FWH4

FWH[3:0]

Start

Load Address in 7 Clocks

CLK

1 Clock

2 Clocks

Address

Sync

TAR

1111b

Tri-State

0000b

Data out 2 Clocks

Data

When internal write complete, the DQ6 will stop toggle.

X,D6,XXb

XXXXb

FWH4

FWH[3:0]

Start

Load Address "An" in 7 Clocks

CLK

1 Clock

2 Clocks

A[15:12]

Load Data "Dn"
in 2 Clocks

D[7:4]

Write the last command(program or erase) to the device in FWH mode.

Address

Sync

TAR

Data

1111b

Tri-State

0000b

A[11:8]

A[7:4]

A[3:0]

D[3:0]

IDSEL

XXXXb

IDSEL

0000b

M Size

XXXXb

XXA[17:16]b

XXXXb

1 Clock

0000b

1110b

1 Clock

0000b

1101b

1 Clock

0000b

1101b

1 Clock

2 Clocks

TAR

1111b

Tri-State

Next Start

1 Clock

2 Clocks

TAR

1111b

Tri-State

Next Start

1 Clock

2 Clocks

TAR

1111b

Tri-State

Next Start

FWH[3:0]

#RESET

W49V002FA

- 26 -

Timing Waveforms for FWH Interface Mode, continued

Boot Block Lockout Enable Timing Diagram

6th Start

Load Address "5555" 7 Clocks

Sync

Internal
program start

TAR

1 Clock

2 Clocks

X101b

Load Data "40"
in 2 Clocks

0100b

Write the 6th command to the device in FWH mode.

0101b

0000b

1111b

Tri-State

0000b

Data

Address

FWH4

FWH[3:0]

1st Start

Load Address "5555" in 7 Clocks

CLK

1 Clock

2 Clocks

X101b

0101b

Load Data "AA"
in 2 Clocks

1010b

Write the 1st command to the device in FWH mode.

FWH4

FWH[3:0]

CLK

FWH4

FWH[3:0]

CLK

FWH4

FWH[3:0]

CLK

Address

Sync

TAR

Data

2nd Start

Load Address "2AAA" in 7 Clocks

1 Clocks

2 Clocks

X010b

1010b

Load Data "55"
in 2 Clocks

0101b

Write the 2nd command to the device in FWH mode.

3rd Start

Load Address "5555" in 7 Clocks

1 Clock

2 Clocks

X101b

0101b

Load Data "80"
in 2 Clocks

1000b

0000b

Write the 3rd command to the device in FWH mode.

Address

Sync

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

1111b

Tri-State

0000b

4th Start

Load Address "5555" in 7 Clocks

1 Clock

2 Clocks

X101b

0101b

Load Data "AA"
in 2 Clocks

1010b

Write the 4th command to the device in FWH mode.

5th Start

Load Address "2AAA" in 7 Clocks

1 Clock

2 Clocks

X010b

1010b

Load Data "55"
in 2 Clocks

0101b

Write the 5th command to the device in FWH mode.

Address

Sync

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

FWH4

FWH[3:0]

CLK

FWH4

FWH[3:0]

CLK

program start

IDSEL

0000b

M Size

XXXXb

Start next
command

1 Clock

2 Clocks

TAR

1111b

Tri-State

Start next
command

1 Clock

2 Clocks

TAR

1111b

Tri-State

Start next
command

1 Clock

2 Clocks

TAR

1111b

Tri-State

Start next
command

1 Clock

2 Clocks

TAR

1111b

Tri-State

Start next
command

1 Clock

2 Clocks

TAR

1111b

Tri-State

Internal

TAR

2 Clocks

1111b Tri-State

1 Clock

0000b

1110b

1 Clock

0000b

1110b

1 Clock

0000b

1110b

1 Clock

0000b

1110b

1 Clock

0000b

1110b

1 Clock

0000b

1110b

#RESET

W49V002FA

Publication Release Date: February 19, 2002

- 27 - Revision A2

Timing Waveforms for FWH Interface Mode, continued

Chip Erase Timing Diagram

Load Address "5555" in 7 Clocks

Sync

Internal
erase start

TAR

1 Clock

X101b

Load Data "10"
in 2 Clocks

0001b

Write the 6th command to the device in FWH mode.

0101b

0000b

1111b

Tri-State

0000b

Data

Address

FWH4

FWH[3:0]

1st Start

CLK

X101b

0101b

1010b

FWH4

FWH[3:0]

CLK

FWH4

FWH[3:0]

CLK

FWH4

FWH[3:0]

CLK

Address

Sync

TAR

Data

Load Address "5555" in 7 Clocks

1 Clock

2 Clocks

Load Data "AA"
in 2 Clocks

Write the 1st command to the device in FWH mode.

Load Address "2AAA" in 7 Clocks

1 Clock

2 Clocks

X010b

1010b

Load Data "55"
in 2 Clocks

0101b

Write the 2nd command to the device in FWH mode.

Load Address "5555" in 7 Clocks

1 Clock

2 Clocks

X101b

0101b

Load Data "80"
in 2 Clocks

1000b

0000b

Write the 3rd command to the device in FWH mode.

Address

Sync

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

1111b

Tri-State

0000b

Load Address "5555" in 7 Clocks

1 Clock

2 Clocks

X101b

0101b

Load Data "AA"
in 2 Clocks

1010b

Write the 4th command to the device in FWH mode.

Load Address "2AAA" in 7 Clocks

1 Clock

2 Clocks

X010b

1010b

Load Data "55"
in 2 Clocks

0101b

Write the 5th command to the device in FWH mode.

Address

Sync

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

FWH4

FWH[3:0]

CLK

FWH4

FWH[3:0]

CLK

2 Clocks

IDSEL

0000b

M Size

XXXXb

Start next
command

1 Clock

2 Clocks

TAR

1111b

Tri-State

Start next
command

1 Clock

2 Clocks

TAR

1111b

Tri-State

Start next
command

1 Clock

2 Clocks

TAR

1111b

Tri-State

Start next
command

1 Clock

2 Clocks

TAR

1111b

Tri-State

Start next
command

1 Clock

2 Clocks

TAR

1111b

Tri-State

Internal
erase start

TAR

2 Clocks

1111b

Tri-State

6th Start

IDSEL

5th Start

IDSEL

4th Start

IDSEL

3th Start

IDSEL

2th Start

IDSEL

1 Clock

0000b

1110b

1 Clock

0000b

1110b

1 Clock

0000b

1110b

1 Clock

0000b

1110b

1 Clock

0000b

1110b

1 Clock

0000b

1110b

#RESET

W49V002FA

- 28 -

Timing Waveforms for FWH Interface Mode, continued

Sector Erase Timing Diagram

6th Start

Load Sector Address in 7 Clocks

Sync

Internal
erase start

1 Clock

SA[15:12]

Load Din
in 2 Clocks

0011b

Write the 6th command(target sector to be erased) to the device in FWH mode.

0000b

TAR

2 Clocks

1111b

Tri-State

0000b

Data

Address

FWH4

FWH[3:0]

1st Start

Load Address "5555" in 7 Clocks

CLK

1 Clock

Start next
command

1 Clock

2 Clocks

1 Clock

X101b

0101b

Load Data "AA"
in 2 Clocks

1010b

Write the 1st command to the device in FWH mode.

FWH4

FWH[3:0]

CLK

FWH4

FWH[3:0]

CLK

FWH4

CLK

Address

Sync

TAR

Data

2nd Start

Load Address "2AAA" in 7 Clocks

1 Clock

Start next
command

1 Clock

2 Clocks

1 Clock

X010b

1010b

Load Data "55"
in 2 Clocks

0101b

Write the 2nd command to the device in FWH mode.

3rd Start

Load Address "5555" in 7 Clocks

1 Clocks

Start next
command

1 Clocks

2 Clocks

1 Clocks

X101b

0101b

Load Data "80"
in 2 Clocks

1000b

0000b

Write the 3rd command to the device in FWH mode.

Address

Sync

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

1111b

Tri-State

0000b

4th Start

Load Address "5555" in 7 Clocks

1 Clock

Start next
command

1 Clock

2 Clocks

1 Clock

X101b

0101b

Load Data "AA"
in 2 Clocks

1010b

Write the 4th command to the device in FWH mode.

5th Start

Load Address "2AAA" in 7 Clocks

1 Clock

Start next
command

1 Clock

X010b

1010b

Load Data "55"
in 2 Clocks

0101b

Write the 5th command to the device in FWH mode.

Address

Sync

2 Clocks

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

FWH4

FWH[3:0]

CLK

FWH4

FWH[3:0]

CLK

XXXXb

IDSEL

Internal
erase start

0000b

1110b

IDSEL

0000b

1110b

IDSEL

0000b

1110b

IDSEL

0000b

1110b

IDSEL

0000b

1110b

IDSEL

0000b

M Size

M
Size

M Size

XXXXb

XXA[17:16]b

XXXXb

TAR

2 Clocks

1111b

Tri-State

2 Clocks

TAR

1111b

Tri-State

2 Clocks

TAR

1111b

Tri-State

2 Clocks

TAR

1111b

Tri-State

2 Clocks

TAR

1111b

Tri-State

2 Clocks

TAR

1111b

Tri-State

1 Clock

0000b

1110b

FWH[3:0]

#RESET

W49V002FA

Publication Release Date: February 19, 2002

- 29 - Revision A2

Timing Waveforms for FWH Interface Mode, continued

FGPI Register/Product ID Readout Timing Diagram

Note: During the GPI read out mode, the DQ[4:0] will capture the states(High or Low) of the FGPI[4:0] input pins. The DQ[7:5] are reserved pins.

#RESET

FWH[3:0]

Start

IDSEL

Load Address "FFBC0100(hex)" in 7 Clocks for GPI Register
& "FFBC0000(hex)/FFBC0001(hex) for Product ID

CLK

1 Clock

Next Start

1 Clock

2 Clocks

1 Clock

0000b

1101b

Address

Sync

TAR

1111b

Tri-State

0000b

Data out 2 Clocks

D[7:4]

Data

0000b

0001b
/0000b

0000b

0000b
/0001b

D[3:0]

A[27:24]

A[23:20] A[19:16]

0000b

M Size

2 Clocks

TAR

1111b

Tri-State

FWH4

Reset Timing Diagram

CLK

VDD

FWH[3:0]

PRST

KRST

RSTP

RST
F

RST

FWH4

#RESET

W49V002FA

- 30 -

ORDERING INFORMATION

PART NO.

ACCESS

TIME

(nS)

POWER SUPPLY

CURRENT MAX.

(mA)

STANDBY V

CURRENT MAX.

(

PACKAGE

W49V002FAP

32L PLCC

W49V002FAQ

32L STSOP

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

HOW TO READ THE TOP MARKING

Example: The top marking of 32L-PLCC W49V002FA

line: winbond logo

line: the part number: W49V002FAP

line: the lot number

line: the tracking code: 132 G H SA

132: Packages made in '01, week 32

G: Assembly house ID: A means ASE, G means Greatek, ...etc.

H: IC revision; A means version A, H means version H, ...etc.

SA: Process code

W49V002FAP

2123055C-082

132GHSA

W49V002FA

Publication Release Date: February 19, 2002

- 31 - Revision A2

PACKAGE DIMENSIONS

32L PLCC

Notes:

D H

Seating Plane

1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based on final
visual inspection sepc.

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in Inches

Dimension in mm

b
c
D

A
A

3.56

0.50

2.80

2.67

2.93

0.71

0.66

0.81

0.41

0.46

0.56

0.20

0.25

0.35

13.89

13.97

14.05

11.35

11.43

11.51

1.27

12.45

12.95

13.46

9.91

10.41

10.92

14.86

14.99

15.11

12.32

12.45

12.57

1.91

2.29

0.004

0.095

0.090

0.075

0.495

0.490

0.485

0.595

0.590

0.585

0.430

0.410

0.390

0.530

0.510

0.490

0.050

0.453

0.450

0.447

0.553

0.550

0.547

0.014

0.010

0.008

0.022

0.018

0.016

0.032

0.026

0.028

0.115

0.105

0.110

0.020

0.140

1.12

1.42

0.044

0.056

0.10

2.41

32L STSOP (8 x 14 mm)

A
A

Min.

Dimension in Inches

Nom. Max.

Min.

Nom. Max.

Symbol

1.20

0.05

0.15

1.05

1.00

0.95

0.17

0.10

0.50

0.00

0.22

0.27

-----

0.21

12.40

8.00

14.00

0.50

0.60

0.70

0.80

0.10

0.047

0.006

0.041

0.040

0.035

0.007

0.009

0.010

0.004

-----

0.008

0.488

0.315

0.551

0.020

0.024

0.028

0.031

0.000

0.004

0.002

A
A

b
c

D
E

Dimension in mm

£c

W49V002FA

- 32 -

VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

April 2001

Initial Issued

Feb. 19, 2002

Modify V

Power Up/Down Detection in Hardware

Data Protection

Modify the description on start in TABLE OF
COMMAND DEFINITION

Delete old flow chart and add embedded algorithm

Add in Input High Voltage for #INIT (V

IHI

) parameter

Change V

(max.) from 0.2 V

DD to

0.3 V

DD;

(min.)

from

0.6 V

0.5 V

DD.

Add the V

IHI/

ILI

for the #INIT pin input spec.

Add HOW TO READ THE TOP MARKING

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,

CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu Chiu, Taipei, 114,

Taiwan, R.O.C.

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