Publication Release Date: April 13, 2005
- 1 -
Revision 1.1
W83195BR-341
Data Sheet
WINBOND
CLOCK GENERATOR
FOR
VIA P4/KT SERIES CHIPSET
W83195BR-341
- II -
Table of Contents-
1.
GENERAL DESCRIPTION ..........................................................................................................1
2.
FEATURES ..................................................................................................................................1
3.
PIN CONFIGURATION ................................................................................................................2
4.
BLOCK DIAGRAM .......................................................................................................................3
5.
PIN DESCRIPTION......................................................................................................................3
5.1
Crystal I/O ........................................................................................................................................4
5.2
CPU, AGP, PCI Clock Outputs .......................................................................................................4
5.3
Fixed Frequency Outputs................................................................................................................5
5.4
DRAM Buffer....................................................................................................................................5
5.5
I2C Control Interface .......................................................................................................................5
5.6
Output Control Pins .........................................................................................................................6
5.7
Power an GND Pins ........................................................................................................................6
6.
FREQUENCY SELECTION BY HARDWARE OR SOFTWARE .................................................7
7.
I
2
C CONTROL AND STATUS REGISTERS................................................................................8
7.1
Register 0: Frequency Select (Default = 08h) ................................................................................8
7.2
Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default: A1h)..........................................8
7.3
Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default: FEh) ....................................................9
7.4
Register 3: REF, 24_48,48,AGP Clock (1 = Enable, 0 = Disable) (Default: F7h).........................9
7.5
Register 4,5 Reserved.....................................................................................................................9
7.6
Register 6: M/N Program (Default: 8Bh).........................................................................................9
7.7
Register 7: M/N Program (Default: 2Fh).......................................................................................10
7.8
Register 8: Spread Spectrum Program (Default: 1Fh).................................................................10
7.9
Register 9: Divider Ratio (Default: 03h) ........................................................................................10
7.10
Register 10: Control (Default: 0Ah)........................................................................................11
7.11
Register 11: Control (Default: E7h)........................................................................................12
7.12
Register 12: Control (Default: 3Ch) .......................................................................................12
7.13
Register 13: Control (Default: 24h) ........................................................................................13
7.14
Register 14: Control (Default: 56h) ........................................................................................13
7.15
Register 15: Slew Rate Control (Default: 55h) ......................................................................13
7.16
Register 16: DRAM Buffer Control (1 = Enable, 0 = Disable) (Default: 7Fh).......................14
7.17
Register 17: Slew Rate Control (Default: CFh) .....................................................................14
7.18
Register 18: M/N Time & Type Control (Default: 5Bh)..........................................................14
7.19
Register 19: Reserved ...........................................................................................................15
7.20
Register 20: Winbond Chip ID (Ready Only) (Default: 61h)..............................................15
W83195BR-341
Publication Release Date: April 13, 2005
- III -
Revision 1.1
7.21
Register 21: Winbond Chip ID (Ready Only) (Default: 50h)..............................................15
8.
ACCESS INTERFACE ...............................................................................................................16
8.1
Block Write Protocol ......................................................................................................................16
8.2
Block Read Protocol......................................................................................................................16
8.3
Byte Write Protocol........................................................................................................................16
8.4
Byte Read Protocol........................................................................................................................16
9.
SPECIFICATIONS .....................................................................................................................17
9.1
Absolute Maximum Ratings ..........................................................................................................17
9.2
General Operating Characteristics ...............................................................................................17
9.3
Skew Group Timing Clock ............................................................................................................17
9.4
CPU 0.7V Electrical Characteristics .............................................................................................18
9.5
CPU 1.0V Electrical Characteristics .............................................................................................18
9.6
AGP Electrical Characteristics ......................................................................................................18
9.7
PCI Electrical Characteristics........................................................................................................19
9.8
24M, 48M Electrical Characteristics .............................................................................................19
9.9
REF Electrical Characteristics.......................................................................................................19
10.
ORDERING INFORMATION......................................................................................................20
11.
HOW TO READ THE TOP MARKING.......................................................................................20
12.
PACKAGE DRAWING AND DIMENSIONS...............................................................................21
13.
REVISION HISTORY .................................................................................................................22
W83195BR-341
Publication Release Date: April 13, 2005
- 1 -
Revision 1.1
1. GENERAL DESCRIPTION
The W83195BR-341 is a Clock Synthesizer for Intel P4 Springdale/Prescott series chipset and support
AMD Athlon processors. W83195BR-341 provides all clocks required for high-speed microprocessor
and provides step-less frequency programming and 32 different frequencies of CPU, AGP, and PCI
clocks setting. All clocks are externally selectable with smooth transitions.
The W83195BR-341 provides I
2
C serial bus interface to program the registers to enable or disable
each clock outputs and provides +/-0.25%, +/-0.5% center type and 0.5%, -1.0% down type spread
spectrum or programmable S.S.T. scale to reduce EMI.
The W83195BR-341 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
2. FEATURES
1 pairs differential clock for CPU (P4 or Athlon)
1 pairs differential clock for Chipset
3 AGP clock outputs
Support two DDR DIMMS or three SDRAM DIMMS
7 PCI synchronous clocks, 1 free running
1 48 MHz clock outputs for USB
1 24_48 MHz for I/O chip, default 24 MHz
2 REF 14.318MHz clock outputs
AGP leads PCICLK from 1.5 nS to 3.5 nS
I
2
C 2-Wire serial interface supports block and byte mode read/write
Step-less frequency programming
Smooth frequency switch with selections from 66 to 200 MHz
Programmable clock outputs Slew rate control and Skew control
+/- 0.25% center type spread spectrum in table mode
Programmable S.S.T. scale to reduce EMI
Programmable registers to enable/stop each output and select modes
Packaged
in
56-pin
SSOP
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