W83301DR-O

Data Sheet Revision History

Pages Dates Version

Version

on Web

Main Contents

1 N.A.

07/2002 1.0

1.0 1

Release

Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet
belong to their respective owners.

LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to
result in personal injury. Winbond customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify
Winbond for any damages resulting from such improper use or sales.

Publication Release Date: Jul., 2002

Revision 1.0

W83301DR-O

1. General

Description

The W83301DR-O is an ACPI-compliant controller for microprocessor and other
computer applications. The part provides functions - two switch controllers to generate a
5V

and a 3.3 V

voltage from ATX power supply; a linear controller STR1 (2.5V

DUAL

and a bus termination controller STR2 (1.25 V

DUAL

) for high-speed bus such as

RDRAM/DDRAM current sinking and sourcing. Besides, the W83301DR-O also can
provide extra voltage up to 0.4V in each regulator output for over-clocking application and
more performance by two hardware pins - V

SET2

, and V

SET3

. In order to reduce the

customer's cost, and simplify the circuit design, the W83301DR-O integrates a charge-
pump engine into the chip to provide higher driving voltage to drive single N-channel
MOSFETs. The W83301DR-O also offers PWOK and over current detection to protect
each output and soft-start protects all linear controllers from rush current attack. The
W83301DR-O is available in a 24-pin TSSOP package.

2. Features

Provides various voltages for DDR-STR applications

Provide a switch controller to generate 5V

DUAL

voltage

Provide a switch controller to generate 3.3V

DUAL

voltage

Linear controller STR12.5V

DUAL

for DDR application

Bus termination controller STR2 1.25V

DUAL

for high speed bus termination

to sink and drive redundant current

Provide a switch 5V

DLEN

pin to enable/disable 5V

output in S5 state for USB

application

Supports DDR ACPI-STR Functions

Drives all N-Channel MOSFETs

Power-Up Softstart for all controllers

Up to 0.4V/0.2V incremental voltage on STR1/STR2 for over-clocking application.

Under-Voltage Fault Monitor

Soft-Start function

24-Pin TSSOP Package

Publication Release Date: Jul., 2002

Revision 1.0

W83301DR-O

4. Pin

Description

SYMBOL PIN

FUNCTION

Reserved

Pin Reserved

DRV

BT Current Source. Connect this pin to the gate of a suitable N-channel
MOSFET for driving bus termination regulator output.

SEN

BT Sense. Connect this pin to the bus termination regulator output.

SINK

BT Current Sink. This pin is used to drive a N-channel MOSFET to sink the
redundant current in the high-speed bus.

Reserved

Function Reserved. Pull up this pin to +5VSB through a 1.5 Kohm resistor.

Vss

Power Ground. Connect this pin to ground.

Power 5V

. Input 5V

supply.

Charge Pump Cap. Attach flying capacitor between this pin and C2 to
generate internally used high voltage from 5V power supply.

Charge Pump Cap. Attach flying capacitor between this pin and C1 to
generate internally used high voltage from 5V power supply.

ChrPmp 10

Charge Pump output. This pin produces voltage doubled 5V supply by
charge pumping. Bypass with a 0.1uF capacitor.

DLEN

5VDL Enable. Control 5V

voltage output. Pull-up internally.

SET3

Voltage Selection. Combine with VSET2 to select output voltages of STR
regulators.

SET2

Voltage Selection. Combine with VSET3 to select output voltages of STR
regulators.

S5#

S5 Signal. Control signal governing the soft off state S5. Pull-up internally.

S3#

S3 Signal. Control signal governing the soft off state S3. Pull-up internally.

SBSEN

Sense. Connect this pin to the STR1 output.

DLSB

Drive. Connect this pin to the gate of a suitable N-channel MOSFET for

driving STR1 output.

DLSB

5VSB Output Control. Connect this pin to the gate of a N-MOSFET to output
5VSB power to 5V

DRV

/5V

DRV

3.3V/5V Output Control. Connect this pin to the gate of a N-MOSFET to
output 3.3V/5V power to 3.3V

/5V

PWOK

Power OK. Open collector input/output. Used to indicate the ready of 5Vin
supply. If any STR supply occurs over current and induce under-voltage,
PWOK will be pull down.

Soft-Start. Attach a capacitor (0.033u) to this pin to determine the softstart
rate. A ramp generated by charging this capacitor with internal soft-start
current (18uA) is used to clamp the voltage rising slew rate of STR regulators
and 5V

. Soft starting avoids too much rush current during voltage setup.

STR1

SEN

STR1 Sense. Connect this pin to the STR1 output.

STR1

DRV

STR1 Drive. Connect this pin to the gate of a suitable N-channel MOSFET for
driving STR1 output.

Reserved

Pin Reserved

Publication Release Date: Jul., 2002

Revision 1.0

W83301DR-O

5. W83301DR-O Dual-Layout with W83301R/W83301DR

VCC3

3.3V

100uF

3.3V

0.1u

5VSB

100uF

MOSFET N

2200uF

0.1u

SET3

0.1u

PWOK

VSET1

MOSFET N

470uF

MOSFET N

1.25V

STR

MOSFET N

5VSB

1.5k

VSET0

SLP_S3#

2.5V

STR

SET2

module

Reserved

DRV

SEN

SINK

Reserved

ChrPmp

S3#

VSET1/3V

SBSEN

VSET0/3V

DLSB

DRV

/5V

DRV

PWOK

STR

SEN1

STR

DRV1

Reserved

DLEN

S5#

VSET3

VSET2

MOSFET N

2200uF

SLP_S5#

3.3V

1.30VSTR

2.9VSTR

20-pin

VSET0

2.6VSTR

2.5VSTR

Bus Termination Controller

1.25VSTR

DDR

2.63VSTR

DDR

2.77VSTR

24-pin

Bus Termination Controller

STR1

Mode

VSET1

1.385VSTR

2.5VSTR

STR1

2.7VSTR

1.35VSTR

1.325VSTR

1.45VSTR

1.25VSTR

VSET2

Mode

VSET3

Publication Release Date: Jul., 2002

Revision 1.0

W83301DR-O

7. Functional

Description

7.1 ACPI State Control

In order to meet the ACPI specification, the W83301DR-O implements an internal state

machine to generate ACPI-compliant power state transition.

There are five states in the state machine, the five states are G3 (Mechanical-Off State),

S0 (Full-Power State), S3 (Sleeping State-Suspend to RAM), S5

(Soft-Off State), S5

Off

and all of the state changes to the other according to the value of S3#, S5# and 5V

DLEN

On the other hand, cause of the W83301DR-O allows the user to disable/enable the 5V

DUAL

output in S5 state via the 5V

DLEN

# pin, there are two states - S5

and S5

Off

, corresponding

to S5 state. Besides, a soft ramp-up mechanism is needed to protect the 5V

output from

the rush current attack during the S5

Off

to S5

state

transition. Same as the 5V

output,

the W83301DR-O also implements soft ramp-up mechanism in each STR outputs during
the S5

state transfers to the S0 state.

As the internal state machine, when the power turns on, the voltage of 5VSB of the ATX

power supply ramps up to 4.5V, the chip will enters the S5

Off

state from the G3 state, and

will enters the S5

state if the signal of 5V

DLEN

#=0 and S5#=0; When the signals S3#=1

and S5#=1, the system will enters the S0 state from S5

off

In the S5

state, the chip will returns back to the S5

Off

state if the 5V

DLEN

#=1 is set.

When the system in the S0 state, the system will enters the S3 (S3#=0, S5#=1) or S5

(S5#=0) state when the system is idle for a long time or user presses the power button.

When the system enters the S3 state, the system will waked up and enter the S0 state

by (S3#=1, S5#=1,PWOK=1), or gets into S5 state by (S5#=0).

Table 1. W83301DR-O Outputs Table

State

STR1

STR2 LUV Activity *

G3 Off

Off

S5 (5V

Off)

Off

(Driven by 3V

DLSB

)

Off Off

S5 (5V

On)

(Driven by 5V

DLSB

)

(Driven by 3V

DLSB

)

Off Off

(Driven by 5V

DRV

)

(Driven by 3V

DRV

)

On On Yes

(Driven by 5V

DLSB

)

(Driven by 3V

DLSB

)

On On Yes

* Only the STR1 has linear under voltage function.

Publication Release Date: Jul., 2002

Revision 1.0

W83301DR-O

7.3 Charge Pump

In order to simply the design circuit and provide a cost-effective solution for customer,

the W83301DR-O integrates with a switched-capacitor voltage doublers charge pump to
provide a higher driving voltage (Up to 10 volt) and can drive single N-channel MOSFETs in
each output.

7.4 Power OK

The W83301DR-O use a bi-direction Power OK signal to ensure the system can work

normally. When the system jump from the state S3 to the state S0, the W83301DR-O will
monitor the input signal from PWOK pin to ensure that external system power is OK and
then will switches each outputs into the S0 state; In the other hand, the W83301DR-O will
pulls down the Power OK signal to inform the system a over current and induce under-
voltage occurred.

7.5 Soft-Start

During the `S5off' to the `S5on' and the `S5on' to the `S0' state transitions, the

5Vdual/3Vdual and STR voltages need to ramp up from 0V to the setting values
respectively. The charging current flowing to output capacitors must be limited to avoid
supply drop-off.

In W83301DR-O, an internal 18 uA current source (Iss) charges an external capacitor

(Css) to generate a linear ramp-up voltage on SS pin (Vss). The Vss slews from 0V to about
9V during the above-mentioned state transitions, and the Vss slew rate is used to clamp the
ramp-up rate of 5Vdual and STR output voltages. This output clamping allows power-ups
free of supply drop-off events.

Since the outputs are ramped up in a constant slew-rate, the current dedicated to

charge any output capacitor can be calculated with the following formula:

COUT

= Iss x (Cout / Css)

Some technique are included in W83301DR-O to further reduce the total charging

current: the bus-terminator is input clamped, and its output voltage slew-rate, so as its
charging current, will be limited to half of that of STR1.

Note that, too slow ramp-up rate is not recommended. If so, the state transition

mentioned above will be prolonged to much. Before Vss ramps up to its upper limit (about
9V), the state transition will not be completed and will not go into next state.

Publication Release Date: Jul., 2002

Revision 1.0

W83301DR-O

8. Electrical

Characteristics

8.1 ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in this table may cause permanent damage to the

device. Precautions should be taken to avoid application of any voltage higher than the
maximum rated voltages to this circuit. Subjection to maximum conditions for extended
periods may affect reliability. Unused inputs must always be tied to an appropriate logic
voltage level (Ground or Vdd).

Symbol Parameter

Rating

Vss, V

Voltage on any pin with respect to GND

- 0.5 V to + 7.0 V

ChrPmp

- 0.5 V to + 12.0 V

Hi-V Pins

Pin# 2,3,4,5,9,10,17,18,19,21,22,23

GND-0.3 V to V

Chr-Pmp

0.3V

Lo-V Pins

Pin# 8,11,12,13,14,15,16,20

GND-0.3 V to Vcc +

0.3V

STG

Storage

Temperature

- 65

°C to + 150°C

Ambient

Temperature

- 55

°C to + 125°C

Operating

Temperature

°C to + 70°C

8.2 AC CHARACTERISTICS

Vcc=5V

± 5 %, T

= 0

°C to +70°C

Parameter

Symbol Min Typ Max

Units

Test Conditions

Vcc SUPPLY CURRENT
Norminal Supply
Current

5VSB

6 mA

POWER-ON RESET
Rising V

5VSB

Threshold

4.3

Chr_Pmp

> 8.5V

5VSB Hysteresis

Rising V

Chr_Pmp

Threshold

8.5

5VSB

> 4.3V

Chr_Pmp

Hysteresis

1 V

SOFT-START
Soft-Start Current

Iss

18 uA

upper limit

9 V

Publication Release Date: Jul., 2002

Revision 1.0

W83301DR-O

8.2 AC CHARACTERISTICS (Continued)

Vcc=5V

± 5 %, T

= 0

°C to +70°C

Parameter

Symbol Min Typ Max Units

Test Conditions

STR1 LINEAR REGULATOR
Nominal Output Voltage

2.5 V Vset2=0V;

Vset3=0V

Nominal Output Voltage

2.63 V Vset2=5V;

Vset3=0V

Nominal Output Voltage

2.77

Vset2=0V; Vset3=5V

Nominal Output Voltage

2.90

Vset2=5V; Vset3=5V

Regulation

STR

SEN1

Under-Voltage Falling

Threshold

80 %

MAX STR

DRV1

Output

Voltage

(STR1

DRV

) < 0.1mA

BUS TERMINATION REGULATOR
Nominal Output Voltage /
V

STRSEN1

50 %

The output is always
the 50% of STR1

Regulation

-2

5VDUAL SWITCH CONTROLLER
5V

DRV

Output High Voltage

Cload=3000p

DRV

Sourcing Current

Cload=3000p

DRV

Sinking Current

400

Cload=3000p

DLSB

Output High Voltage

Cload=3000p

DLSB

Sourcing Current

Cload=3000p

DLSB

Sinking Current

230

Cload=3000p

SWITCH CONTROLLER

DRV

Output High Voltage

Cload=3000p

DRV

Sourcing Current

Cload=3000p

DRV

Sinking Current

400

Cload=3000p

3.3V

LINEAR REGULATOR

Nominal Output Voltage

3.3

Regulation

STR

SEN1

Under-Voltage Falling

Threshold

80 %

MAX 3.3V

DLSB

Output

Voltage

(3.3V

DLSB

) < 0.1mA

S3#,S5#,5VDLEN#, PWOK,CHARGE PUMP
Input Logic High

2.2

Input Logic Low

0.8

PWOK Output Inpedence

150

ohm LUV active

Charge Pump Frequency

200

KHz

Publication Release Date: Jul., 2002

Revision 1.0

W83301DR-O

10. Ordering Information

Part Number

Package Type

Production Flow

W83301DR-O

24-PIN TSSOP

Commercial, 0

°C to +70°C

11. How to Read the Top Marking

1st line: Winbond logo

2nd line: W83301DR-O the part number
3rd line: Tracking code Tracking code 106 O B 1 1039050-21NA
106: packages made in Year 01', week 6
O: assembly house ID; O means OSE, G means GR, ...
B: the IC version
1: wafers manufactured in Winbond FAB I
1039050-21NA: wafer production series number

Headquarters

No. 4, Creation Rd. III

Science-Based Industrial Park
Hsinchu, Taiwan

TEL: 886-35-770066
FAX: 886-35-789467

www: http://www.winbond.com.tw/

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan

TEL: 886-2-7190505

FAX: 886-2-7197502
TLX: 16485 WINTPE

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong

Kowloon, Hong Kong

TEL: 852-27516023-7
FAX: 852-27552064

Winbond Electronics
(North America) Corp.

2730 Orchard Parkway

San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666

FAX: 1-408-9436668

Please note that all data and specifications are subject to change without notice. All the
trademarks of products and companies mentioned in this data sheet belong to their respective
owners.
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sale.

W83301DR-O

1060B11039050-21NA

inbond

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