Document Outline
- WM2618
- Dual 12-bit Serial Input Voltage Output DAC
- Production Data, October 2000, Rev 1.1
- FEATURES
- DESCRIPTION
- APPLICATIONS
- ORDERING INFORMATION
- BLOCK DIAGRAM
- TYPICAL PERFORMANCE
- PIN CONFIGURATION
- PIN DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL PERFORMANCE GRAPHS
- DEVICE DESCRIPTION
- GENERAL FUNCTION
- SERIAL INTERFACE
- SOFTWARE CONFIGURATION OPTIONS
- PACKAGE DIMENSIONS
WM2618
Dual 12-bit Serial Input Voltage Output DAC
Production Data, October 2000, Rev 1.1
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Production Data datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics' Terms and Conditions.
2000 Wolfson Microelectronics Ltd
.
FEATURES
Two 12-bit voltage output DACs
Single supply from 2.7V to 5.5V supply operation
DNL
0.5 LSB, INL
1.9
Low power consumption
- 3mW typical in slow mode
- 8mW typical in fast mode
TMS320, (Q)SPI
, and Microwire
compatible
serial interface
Programmable settling time 4
s or 12
s typical
APPLICATIONS
Battery powered test instruments
Digital offset and gain adjustment
Battery operated/remote industrial controls
Machine and motion control devices
Cellular telephones
Wireless telephone and communication systems
Speech synthesis
Arbitrary waveform generation
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM2618CD
0 to 70C
8-pin SOIC
WM2618ID
-40 to 85C
8-pin SOIC
DESCRIPTION
The WM2618 is a dual 12-bit voltage output, resistor string,
digital-to-analogue converter. A power-on-reset function
ensures repeatable start-up conditions.
The device has been designed to interface efficiently to industry
standard microprocessors and DSPs, including the TMS320
family. The WM2618 is programmed with a 16-bit serial word.
The WM2618 has a simple-to-use single 2.7V to 5.5V supply.
The digital inputs feature Schmitt triggers for high noise
immunity.
The number of clocks from the falling edge of NCS are counted
automatically. The device is then updated and disabled from
accepting further data inputs.
Excellent performance is delivered with a typical DNL of 0.5
LSBs. The settling time of the DAC is programmable to allow
the designer to optimise speed versus power dissipation.
The device is available in an 8-pin SOIC package ideal for
space-critical applications. Commercial temperature (0 to
70C) and Industrial temperature (-40 to 85C) variants are
supported.
BLOCK DIAGRAM
TYPICAL PERFORMANCE
(7) OUTB
(4) OUTA
12-BIT
DAC B
HOLDING
LATCH
12-BIT
DAC A
LATCH
REFIN(6)
POWER-ON
RESET
DIN (1)
SCLK (2)
NCS (3)
(5)
AGND
VDD
(8)
POWERDOWN/
SPEED
CONTROL
12-BIT
DAC B
CONTROL
LATCH
DAC
OUTPUT
BUFFER
2-BIT
CONTROL
LATCH
X1
X1
X2
X2
DAC
OUTPUT
BUFFER
REFERENCE
INPUT BUFFER
REFERENCE
INPUT BUFFER
WM2618
16-BIT
SHIFT
REGISTER
AND
CONTROL
LOGIC
data
5V = VDD, V
REF
= 2.048V, Speed = Fast mode, Load = 10k/100pF
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
512
1024
1536
2048
2559
3071
3583
4095
DIGITAL CODE
DNL
-
L
S
B
WM2618
Production Data
WOLFSON MICROELECTRONICS LTD
PD
Rev 1.1 October 2000
2
PIN CONFIGURATION
1
2
3
4
NCS
DIN
SCLK
AGND
REFIN
OUTB
VDD
OUTA
5
6
7
8
PIN DESCRIPTION
PIN NO
NAME
TYPE
DESCRIPTION
1
DIN
Digital input
Serial data input.
2
SCLK
Digital input
Serial clock input.
3
NCS
Digital input
Chip select. This pin is active low.
4
OUTA
Analogue output
DAC A analogue output.
5
AGND
Supply
Analogue ground.
6
REFIN
Analogue input
Voltage reference input.
7
OUTB
Analogue output
DAC B analogue output
8
VDD
Supply
Positive power supply.
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
MIN
MAX
Supply voltage, VDD to AGND
7V
Digital input voltage
-0.3V
VDD + 0.3V
Reference input voltage
-0.3V
VDD + 0.3V
Operating temperature range, T
A
WM2618C
WM2618I
0
C
-40
C
70
C
85
C
Storage temperature
-65
C
150
C
Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds
260
C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage
VDD
2.7
5.5
V
High-level digital input voltage
V
IH
2
V
Low-level digital input voltage
V
IL
0.8
V
Reference voltage to REFIN
V
REF
VDD - 1.5
V
Load resistance
R
L
2
k
Load capacitance
C
L
100
Serial clock rate
fSCLK
20
WM2618C
0
70
C
Operating free-air temperature
T
A
WM2618I
-40
85
C
Note: Reference voltages greater than VDD/2 will cause saturation for large DAC codes.
Production Data
WM2618
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 October 2000
3
ELECTRICAL CHARACTERISTICS
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
10%, V
REF
= 2.048V and VDD
= 3V
10%, V
REF
= 1.024V over recommended operating
free-air temperature range (unless noted otherwise)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static DAC Specifications
Resolution
12
bits
Integral non-linearity
INL
See Note 1
1.9
4
LSB
Differential non-linearity
DNL
See Note 2
0.5
1
LSB
Zero code error
ZCE
See Note 3
3
12
mV
Gain error
GE
See Note 4
0.1
0.6
% FSR
D.c. power supply rejection ratio
DC PSRR
See Note 5
0.5
mV/V
Zero code error temperature coefficient
See Note 6
10
ppm/
C
Gain error temperature coefficient
See Note 6
10
ppm/
C
DAC Output Specifications
Output voltage range
0
VDD - 0.1
V
Output load regulation
2k
to 10k
load
See Note 7
0.1
0.3
%
Power Supplies
Active supply current
I
DD
No load, V
IH
= VDD, V
IL
= 0V
VDD = 5.5V, V
REF
= 2.048V Slow
VDD
= 5.5V, V
REF
= 2.048V Fast
See Note 8
0.6
1.6
1.0
2.5
mA
mA
Power down supply current
No load,
all digital inputs 0V or VDD
0.01
A
Dynamic DAC Specifications
Slew rate
AC code 128 to 4095, 10%-90%
Slow
Fast
See Note 9
0.3
2.4
0.5
3.0
V/
s
V/
s
Settling time
DAC code 128 to 4095
Slow
Fast
See Note 10
12.0
4.0
s
s
Glitch energy
Code 2047 to 2048
10
nV-s
Reference
Reference input resistance
R
REFIN
10
M
Reference input capacitance
C
REFIN
5
pF
Reference feedthrough
V
REF
= 1VPP at 1kHz
+ 1.024V dc, DAC code 0
-60
dB
Reference input bandwidth
V
REF
= 0.2VPP + 1.024V dc
DAC code 2048
Slow
Fast
0.5
1.0
MHz
MHz
Digital Inputs
High level input current
I
IH
Input voltage = VDD
1
A
Low level input current
I
IL
Input voltage = 0V
-1
A
Input capacitance
C
I
8
pF
WM2618
Production Data
WOLFSON MICROELECTRONICS LTD
PD
Rev 1.1 October 2000
4
Notes:
1.
Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale
(excluding the effects of zero code and full scale errors).
2.
Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any
adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or
remains constant) as a change in digital input code.
3.
Zero code error is the voltage output when the DAC input code is zero.
4.
Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.
5.
Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this
signal imposed on the zero code error and the gain error.
6.
Zero code error and Gain error temperature coefficients are normalised to full scale voltage.
7.
Output load regulation is the difference between the output voltage at full scale with a 10k
load and 2k
load. It
is expressed as a percentage of the full scale output voltage with a 10k
load.
8.
I
DD
is measured while continuously writing code 2048 to the DAC. For V
IH
< VDD - 0.7V and V
IL
> 0.7V supply
current will increase.
9.
Slew rate results are for the lower value of the rising and falling edge slew rates.
10.
Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising
and falling edges. Limits are ensured by design and characterisation, but are not production tested.
SERIAL INTERFACE
NCS
SCLK
DIN
D15
D14
D13
D12
D11
D0
t
SUCSS
t
WCL
t
WCH
t
SUCS1
t
SUCS2
t
HDCLK
t
SUDCLK
Figure 1 Timing Diagram
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
10%, V
REF
= 2.048V and VDD
= 3V
10%, V
REF
= 1.024V over recommended
operating free-air temperature range (unless noted otherwise)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
SUCSS
Setup time NCS low before SCLK low
5
ns
t
SUSCS1
Setup time, falling edge of SCLK to rising edge of
NCS, external end of write
10
ns
t
SUSCS2
Setup time, rising edge of SCLK to falling edge of
NCS, start of next write cycle
5
ns
t
WCL
Pulse duration, SCLK high
25
ns
t
WCH
Pulse duration, SCLK low
25
ns
t
SUDCLK
Setup time, data ready before SCLK falling edge
5
ns
t
HDCLK
Hold time, data held valid after SCLK falling edge
5
ns
Production Data
WM2618
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 October 2000
5
TYPICAL PERFORMANCE GRAPHS
5V = VDD, V
REF
= 2.048V, Speed = Fast mode, Load = 10k/100pF
-3
-2
-1
0
1
2
3
0
512
1024
1536
2048
2559
3071
3583
4095
DIGITAL CODE
I
N
L - LS
B
Figure 2 Integral Non-Linearity
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0
1
2
3
4
5
6
7
8
9
10
ISINK- mA
OU
TP
U
T
V
O
LTA
GE
-
V
Slow
Fast
VDD = 3V, V
REF
= 1V, Input Code = 0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0
1
2
3
4
5
6
7
8
9
10
ISINK - mA
OU
TP
U
T
V
O
LTA
GE
-
V
Slow
Fast
VDD = 5V, V
REF
= 2V, Input Code = 0
Figure 3 Sink Current VDD = 3V
Figure 4 Sink Current VDD = 5V
2.02
2.025
2.03
2.035
2.04
2.045
2.05
2.055
2.06
0
1
2
3
4
5
6
7
8
9
10
11
ISOURCE- mA
OU
TP
U
T
V
O
LTA
GE
-
V
Slow
Fast
VDD = 3V, V
REF
= 1V, Input Code = 4095
4.06
4.065
4.07
4.075
4.08
4.085
4.09
4.095
4.1
0
1
2
3
4
5
6
7
8
9
10
11
ISOURCE - mA
OU
TP
U
T
V
O
LTA
GE
-
V
Slow
Fast
VDD = 5V, V
REF
= 2V, Input Code = 4095
Figure 5 Source Current VDD = 3V
Figure 6 Source Current VDD = 5V
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