Document Outline

• Features
• Applications
• Description
  • Figure 1 - Functional Block Diagram
• Changes Summary
  • Figure 2 - 27mm x 27mm PBGA (JEDEC MO-151) Pinout
• 1.0 Device Overview
• 2.0 Functional Description
• 3.0 Frame Alignment Timing
  • Figure 3 - CT-Bus Timing for 8Mb/s Backplane Data Streams
  • Figure 4 - ST-Bus Timing for 16Mb/s Backplane Data Streams
• 4.0 Switching Configuration
  • 4.1 Backplane Interface
  • 4.2 Local Interface
    • Table 1 - Mode Selection for Backplane Streams
    • Table 2 - Mode Selection for Local STi0 - 3 and STo0 - 3 Streams, Group 0
    • Table 3 - Mode Selection for Local STi4 - 7 and STo4 - 7 Streams, Group 1
    • Table 4 - Mode Selection for Local STi8 - 11 and STo8 - 11 Streams, Group 2
    • Table 5 - Mode Selection for Local STi12 - 15 and ST012 - 15 Streams, Group 3
    • Table 6 - Mode Selection for Local STi16 - 27 and STo16 - 27 Streams, Group 4
• 5.0 Local Input Delay Selection
• 6.0 Output Advancement Selection
• 7.0 Local Output Timing Considerations
• 8.0 Memory Block Programming
• 9.0 Delay Through the MT90866
  • 9.1 Variable Delay Mode
    • Figure 5 - Block Programming Data in the Connection Memories
  • 9.2 Constant Delay Mode
• 10.0 Microprocessor Interface
  • 10.1 DTA Data Transfer Acknowledgment Pin
• 11.0 Address Mapping of Memories and Registers
  • Table 7 - Address Map For Internal Registers (A13 = 0) (continued)
  • Table 8 - Address Map for Memory Locations (A13 = 1)
• 12.0 Backplane Connection Memory
• 13.0 Local Connection Memory
• 14.0 Bit Error Rate Test
• 15.0 External Tristate Control
  • 15.1 BCSTo Control Stream
    • Figure 6 - Backplane Control (BCSTo) Timing when the STio data rate is 8Mb/s
    • Figure 7 - Backplane Control (BCSTo) Timing when the STio data rate is 16Mb/s
  • 15.2 LCSTo Control Stream
    • Figure 8 - Local Control (LCSTo) Timing when STo0-18 are operated at 8Mb/s
    • Figure 9 - Local Control (LCSTo) Timing when STo0-18 are operated at 4Mb/s
    • Figure 10 - Local Control (LCSTo) Timing when all STo0-27 are operated at 2 Mb/s
    • Figure 11 - Example of Local Control (LCSTo) Timing when the Local Streams have Different Data Rates
• 16.0 DPLL
  • 16.1 MT90866 Modes of Operation
    • Figure 12 - Typical Timing Control Configuration
    • 16.1.1 Primary Master Mode
    • 16.1.2 Secondary Master Mode
    • 16.1.3 Slave Mode
• 17.0 DPLL Functional Description
  • Figure 13 - DPLL Functional Block Diagram
  • 17.1 Reference Select and Frequency Mode MUX Circuits
  • 17.2 PRI and SEC MUX Circuits
  • 17.3 Frame Select MUX
  • 17.4 CT Clock and Frame Monitor Circuits
  • 17.5 Reference Monitor Circuits
  • 17.6 State Machine Circuit
    • Figure 14 - State Machine Diagram
• 18.0 Phase Locked Loop (PLL) Circuit
  • Figure 15 - Block Diagram of the PLL Module
  • 18.1 Skew Control
    • Figure 16 - Skew Control Circuit Diagram
  • 18.2 Maximum Time Interval Error (MTIE)
  • 18.3 Phase Detector
  • 18.4 Phase Offset Adder
  • 18.5 Phase Slope Limiter
  • 18.6 Loop Filter
  • 18.7 Digitally Controlled Oscillator (DCO)
  • 18.8 Divider
  • 18.9 Frequency Select MUX Circuit
  • 18.10 Modes of Operation
    • 18.10.1 Normal Mode
    • 18.10.2 Holdover Mode
    • 18.10.3 Freerun Mode
• 19.0 Measures of Performance
  • 19.1 Intrinsic Output Jitter
  • 19.2 Jitter Tolerance
  • 19.3 Jitter Transfer
    • Figure 17 - DPLL Jitter Transfer Function Diagram - wide range of frequencies
    • Figure 18 - Detailed DPLL Jitter Transfer Function Diagram
  • 19.4 Frequency Accuracy
  • 19.5 Holdover Frequency Stability
  • 19.6 Locking Range
  • 19.7 Phase Slope
  • 19.8 Maximum Time Interval Error (MTIE)
  • 19.9 Phase Lock Time
• 20.0 Initialization of the MT90866
• 21.0 JTAG Support
  • 21.1 Test Access Port (TAP)
  • 21.2 Instruction Register
  • 21.3 Test Data Register
  • 21.4 BSDL
• 22.0 Register Descriptions
  • Table 9 - Control Register (CR) Bits (continued)
  • Table 10 - Device Mode Selection (DMS) Register Bits (continued)
  • Table 11 - Block Programming Mode (BPM) Register Bits (continued)
  • Table 12 - Local Input Bit Delay Registers (LIDR0 to LIDR9) Bits
  • Table 13 - Local Input Bit Delay Programming (continued)
  • Figure 19 - Local Input Bit Delay Timing
  • Table 14 - Backplane Output Advancement Registers (BOAR0 to BOAR3) Bit
  • Figure 20 - Example of Backplane Output Advancement Timing
  • Table 15 - Local Output Advancement Registers (LOAR0 to LOAR3) Bits
  • Figure 21 - Local Output Advancement Timing
  • Table 16 - Local Bit Error Rate Input Selection (LBIS) Register Bits
  • Table 17 - Local Bit Error Rate Register (LBERR) Bits
  • Table 18 - Backplane Bit Error Rate Input Selection (BBIS) Register Bits
  • Table 19 - Backplane Bit Error Rate Register (BBERR) Bits
  • Table 20 - DPLL Operation Mode (DOM1) Register Bits (continued)
  • Table 21 - DPLL Operation Mode (DOM2) Register Bits (continued)
  • Table 22 - MT90866 Mode Selection - By Programming DOM1 and DOM2 Registers
  • Table 23 - DPLL Output Adjustment (DPOA) Register Bits
  • Table 24 - DPLL House Keeping (DHKR) Register Bits (continued)
  • Table 25 - Backplane Connection Memory Bits
  • Table 26 - BSAB and BCAB Bits Usage when Source Streams are from the Local Port
  • Table 27 - BSAB and BCAB Bits Usage when Source Streams are from the Backplane Port
  • Table 28 - Local Connection Memory High Bits
  • Table 29 - Local Connection Memory Low Bits (continued)
  • Table 30 - LSAB and LCAB Bits Usage when Source Streams are from the Backplane Port
  • Table 31 - LSAB and LCAB Bits Usage when Source Stream are from the Local Port
• 23.0 DC/AC Electrical Characteristics
  • Figure 22 - Backplane Frame Pulse Input and Clock Input Timing Diagram
  • Figure 23 - Backplane Frame Pulse Output and Clock Output Timing Diagram (in Primary Master Mode ...
  • Figure 24 - Backplane Frame Pulse Input and Clock Input Timing Diagram
  • Figure 25 - Reference Input Timing Diagram when the input frequency = 8 kHz
  • Figure 26 - Reference Input Timing Diagram when the input frequency = 2.048 MHz
  • Figure 27 - Reference Input Timing Diagram when the input frequency = 1.544 Hz
  • Figure 28 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
  • Figure 29 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
  • Figure 30 - Reference Input Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
  • Figure 31 - Reference Output Timing Diagram when (DIV1, DIV0) = (1, 0) in DOM2 Register
  • Figure 32 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 1) in DOM2 Register
  • Figure 33 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 4.096 MHz
  • Figure 34 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 8.192 MHz
  • Figure 35 - Local Clock Timing Diagram when ST_CKo frequency = 16.384 MHz
  • Figure 36 - C1M5o Output Clock Timing Diagram
  • Figure 37 - Backplane Serial Stream Timing when the Data Rate is 8 Mb/s
  • Figure 38 - Backplane Serial Stream Timing when the Data Rate is 16 Mb/s
  • Figure 39 - Local Serial Stream Output Timing
  • Figure 40 - Local Serial Stream Input Timing
  • Figure 41 - Local Serial Output and External Control
  • Figure 42 - Backplane Serial Output and External Control
  • Figure 43 - Output Driver Enable (ODE)
  • Figure 44 - Motorola Non-Multiplexed Bus Timing
  • Figure 45 - JTAG Test Port Timing Diagram
  • Figure 46 - Reset Pin Timing Diagram
• 24.0 Trademarks