Document Outline

• Features
• Applications
• Description
• Variants
  • Table 1 - Variant Options
• Related Documents
  • Table 2 - Related Documents
  • Table 3 - Referenced Documents
  • Figure 1 - MT90880 High Level Overview
• 1.0 Changes Summary
• 2.0 Physical Specification
  • Figure 2 - Package View and Ball Positions
• 3.0 External Interface Description
  • 3.1 WAN Access Interface
    • Table 4 - WAN Access Interface
  • 3.2 Local TDM Interface
    • Table 5 - Local TDM Interface
  • 3.3 Packet Interfaces
    • 3.3.1 MII Interfaces
      • Table 6 - MII Interfaces
    • 3.3.2 RMII Interfaces
      • Table 7 - RMII Interface
  • 3.4 PCI Interface
    • Table 8 - PCI Interface
  • 3.5 External Memory Interface
    • Table 9 - External Memory Interface
  • 3.6 System Control Interface
    • Table 10 - System Control Interface
  • 3.7 Test Facilities
    • 3.7.1 JTAG Interface
      • Table 11 - JTAG Interface
    • 3.7.2 Test Facility
      • Table 12 - Test Facilities
    • 3.7.3 Test Operating Modes
      • Table 13 - Bootstrap Pin Functions
  • 3.8 Power and Ground Connections
    • Table 14 - Power and Ground Connections
• 4.0 Typical Applications
  • 4.1 Packet Backplane Interconnection
    • Figure 2 - Multiservice Access Platform using the MT90880
  • 4.2 Circuit Emulation Services
    • Figure 3 - Circuit Emulation Services over the packet network
  • 4.3 Internet Off-load
    • Figure 4 - Internet Off-load solution using the MT90880
  • 4.4 Remote Access Concentration
    • Figure 5 - Remote Access Concentrator using the MT90880
  • 4.5 Local Resource Pool Example
    • Figure 6 - Use of a Local Resource Pool
  • 4.6 H.100/H.110 Extension
    • Figure 7 - H.100/H.110 Extension over Ethernet link
  • 4.7 H.100/H.110 Expansion
    • Figure 8 - H.100/H.110 Expansion using Ethernet Switching Fabric
• 5.0 Functional Operation
  • 5.1 Overview
    • Figure 9 - MT9088x Family Operation
  • 5.2 Basic Operation
    • Figure 10 - MT90880 Data and Control Flows
    • 5.2.1 WAN Access Interface
      • 5.2.1.1 TDM Packet Assembly
    • 5.2.2 Packet Transmission
    • 5.2.3 CPU Packet Generation
    • 5.2.4 Packet Reception
    • 5.2.5 Call Setup and Control
  • 5.3 Data and Control Flows
    • Figure 11 - WAN to Packet Data and Control Flow
    • Figure 12 - Packet to WAN Data Flow
    • Figure 13 - WAN to Packet Data Flow via Local Resource
    • Figure 14 - Packet to WAN Data Flow via Local Resource
    • Figure 15 - PCI to Packet Data Flow
    • Figure 16 - Packet to PCI Data Flow
  • 5.4 Packet Assembly
    • 5.4.1 Payload Order
      • Figure 17 - Channel and stream order for packet formation
    • 5.4.2 Packet Structure
      • Figure 18 - Packet Structure for MT9088x Family
    • 5.4.3 Context Descriptor Protocol
      • Figure 19 - Context Descriptor Field
  • 5.5 Context Negotiation and Establishment
    • 5.5.1 Overview
    • 5.5.2 New Context Establishment
      • Table 15 - New Context Establishment
    • 5.5.3 Context Modification (Addition or deletion of physical channels)
      • Table 16 - Context Modification Process
    • 5.5.4 Context Removal
      • Table 17 - Context Teardown Process
    • 5.5.5 Context Cleardown
• 6.0 Functional Block Descriptions
  • 6.1 WAN Interface and Multiplexers
    • 6.1.1 Port Data Formats
      • Table 18 - Input Data Formats accepted by the MT9088x family
    • 6.1.2 Operational Modes
      • Figure 20 - Connecting to Framers in Synchronous Master Mode
      • Figure 21 - Connecting to an H.100/H.110 Backplane in Synchronous Slave Mode
      • Figure 22 - Connecting Framers to the MT90880 in Asynchronous Mode
  • 6.2 TDM Cross-Connect Switch
    • Figure 23 - TDM Switch Access Multiplexers
    • 6.2.1 Multiplexing and Blocking
    • 6.2.2 Re-ordering Timeslots
    • 6.2.3 Channel Broadcast
  • 6.3 WAN Receive and Transmit Functions
  • 6.4 Operation of the WAN Receive Block
    • Figure 24 - Operation of the WAN Receive Controller
    • 6.4.1 Context Control in the WAN Receive/Transmit Controllers
      • Figure 25 - Context Look-Up Table
    • 6.4.2 Jitter Buffer Operation
  • 6.5 Queue Manager
    • 6.5.1 Queues to the Packet Interface
      • Table 19 - Configuration of Packet Queues
      • Table 20 - Example of Weighted Fair Queuing
    • 6.5.2 Queues to PCI Interface
    • 6.5.3 Queues to WAN Interface
  • 6.6 Packet Transmit
    • 6.6.1 Protocol Stacks
    • 6.6.2 Shadow Headers
  • 6.7 Ethernet MAC
  • 6.8 Packet Classification
    • 6.8.1 Pattern Matching
      • Figure 26 - Packet Classification Process
    • 6.8.2 Example Classification Scheme
      • Table 21 - Pattern Matching for Example Traffic Class 1
      • Table 22 - Control Register Fields for Example Traffic Class 1
      • Table 23 - Pattern Matching for Example Traffic Class 2
      • Table 24 - Control Register Fields for Example Traffic Class 2
      • Table 25 - Pattern Matching for Example Traffic Class 3
      • Table 26 - Control Register Fields for Example Traffic Class 3
      • Table 27 - Pattern Matching for Example Traffic Class 4 
      • Table 28 - Control Register Fields for Example Traffic Class 4
  • 6.9 Memory Management Unit
    • 6.9.1 External Memory Requirements
      • Figure 27 - PDV Supported for Different Memory and Packet Payload Sizes
    • 6.9.2 Granule Structure
    • 6.9.3 Connecting the MT9088x to External Memory
      • Figure 28 - Connecting the MT90880 to a Single External Memory Device
      • Table 29 - Total Available Memory Size, Using Four External SSRAM Devices
      • Figure 29 - Connecting the MT90880 to Multiple External Memory Devices
    • 6.9.4 External Memory Interface Timing
  • 6.10 PCI Interface
    • 6.10.1 Address and Data Width support
    • 6.10.2 Target Transaction Support
    • 6.10.3 Master Support
    • 6.10.4 Configuration and Registers
      • Figure 30 - MT90880 Memory and Register Space Organization
    • 6.10.5 Signalling Environment
    • 6.10.6 Open Drain Circuitry
      • Figure 31 - pci_serr#, pci_inta# Open Drain Circuitry
  • 6.11 DMA Controller
    • Figure 32 - DMA Transfer to/from System Memory
    • 6.11.1 DMA Descriptor Rings and Lists
      • Figure 33 - Descriptor Ring Structure
      • Figure 34 - Descriptor List Structure
    • 6.11.2 Data Transfer from CPU to MT90880
    • 6.11.3 Data Transfer from MT90880 to CPU
      • Figure 35 - DMA Operation from CPU Packet Queues
  • 6.12 Board Level Test Features
    • 6.12.1 JTAG Support
    • 6.12.2 Test Access Port (TAP)
    • 6.12.3 Test Access Registers
  • 6.13 DPLL Specification
    • 6.13.1 Master Mode
      • Figure 36 - DPLL Jitter Transfer Function Diagram Across a Wide Range of Frequencies
      • Figure 37 - Detailed DPLL Jitter Transfer Function Diagram
    • 6.13.2 Slave Mode
    • 6.13.3 Free-run Mode
    • 6.13.4 DPLL Performance Parameters
      • Table 30 - DPLL Performance Parameters
• 7.0 Memory Map and Register definitions
• 8.0 Special Note to Users: MT9088x handling of received corrupted Ethernet packets and dealing wi...
  • 8.1 Issue
  • 8.2 Recommendation
• 9.0 DC Characteristics
  • Absolute Maximum Ratings - Voltage measurements are with respect to ground (VSS) unless otherwise...
  • Recommended Operating Conditions - Voltage measurements are with respect to ground (VSS) unless o...
  • DC Characteristics
  • 9.0.1 Input Levels
  • 9.0.2 Output Levels
• 10.0 AC Characteristics
  • 10.1 WAN Access Interface
    • 10.1.1 Slave Clock Mode
      • Table 31 - WAN Access Interface Timing - Slave Mode
      • Figure 38 - WAN Bus Slave Mode Timing at 2.048 Mbs
      • Figure 39 - WAN Bus Slave Mode Timing at 2.048 Mbs Generic E1 Mode
      • Figure 40 - WAN Bus Slave Timing at 8.192 Mbs
    • 10.1.2 Clock Master Mode
      • Table 32 - WAN Access Interface Timing - Master Mode
      • Figure 41 - WAN Bus Clock Master Mode Timing at 2.048 Mbs
      • Figure 42 - WAN Bus Clock Master Mode at 2.048 Mbs - Generic E1 Mode
      • Figure 43 - WAN Bus Clock Master Mode Timing at 8.192Mbs
  • 10.2 Local TDM Interface
    • Table 33 - Local TDM Interface Timing
    • Figure 44 - Local Bus Timing at 2.048 Mbs
    • Figure 45 - Local Bus Timing at 4.096Mbs
    • Figure 46 - Local Bus Timing at 8.192 Mbs
  • 10.3 Packet Interface
    • 10.3.1 MII Transmit
      • Table 34 - Packet Interface Timing - MII Transmit
    • 10.3.2 MII Receive
      • Table 35 - Packet Interface Timing - MII Receive
      • Figure 48 - MII Port Receive Characteristics
    • 10.3.3 RMII Interface
      • Table 36 - Packet Interface Timing - RMII Interface
  • 10.4 External Memory Interface
    • Table 37 - External Memory Timing
    • Figure 49 - External RAM Single Cycle Read
    • Figure 50 - External RAM Multi Cycle Read
    • Figure 51 - External RAM Single Cycle Write
    • Figure 52 - External RAM Multi Cycle Write
  • 10.5 System Control Port
    • Table 38 - System Clock
  • 10.6 JTAG Interface
    • Table 39 - JTAG Interface
    • Figure 53 - JTAG Clock and Reset Timing
• 11.0 Glossary