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Электронный компонент: MT93L00A

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1
Features
Independent multiple channels of echo
cancellation; from 32 channels of 64ms to 16
channels of 128ms with the ability to mix
channels at 128ms or 64ms in any combination
Independent Power Down mode for each group
of 2 channels for power management
ITU-T G.165 and G.168 compliant
Field proven, high quality performance
Compatible to ST-BUS and GCI interface at
2Mb/s serial PCM
PCM coding,
/A-Law ITU-T G.711 or sign
magnitude
Per channel Fax/Modem G.164 2100Hz or
G.165 2100Hz phase reversal Tone Disable
Per channel echo canceller parameters control
Transparent data transfer and mute
Fast reconvergence on echo path changes
Non-Linear Processor with high quality
subjective performance
Protection against narrow band signal
divergence
Offset nulling of all PCM channels
10 MHz or 20 MHz master clock operation
3.3 V pads and 1.8V Logic core operation with
5-Volt tolerant inputs
No external memory required
Non-multiplexed microprocessor interface
IEEE-1149.1 (JTAG) Test Access Port
Applications
Voice over IP network gateways
Voice over ATM, Frame Relay
T1/E1/J1 multichannel echo cancellation
Wireless base stations
Echo Canceller pools
DCME, satellite and multiplexer systems
Description
The MT93L00 Voice Echo Canceller implements a
cost effective solution for telephony voice-band echo
cancellation conforming to ITU-T G.168
requirements. The MT93L00 architecture contains
16 groups of two echo cancellers (ECA and ECB)
which can be configured to provide two channels of
64 milliseconds or one channel of 128 milliseconds
echo cancellation. This provides 32 channels of 64
milliseconds to 16 channels of 128 milliseconds echo
cancellation or any combination of the two
configurations. The MT93L00 supports ITU-T G.165
and G.164 tone disable requirements.
Figure 1 - Functional Block Diagram
RESET
Rout
IC0
Sout
DS CS R/W A10-A0 DTA D7-D0
Echo Canceller Pool
V
SS
V
DD1 (3.3V)
TDI TDO TCK TRST
TMS
Rin
IRQ
C4i
F0i
MCLK
ODE
Sin
Fsel
Test Port
Microprocessor Interface
Timing
Unit
Serial
to
Parallel
Parallel
to
Serial
PLL
Group 0
ECA/ECB
Group 4
ECA/ECB
Group 8
ECA/ECB
Group 12
ECA/ECB
Group 1
ECA/ECB
Group 5
ECA/ECB
Group 9
ECA/ECB
Group 13
ECA/ECB
Group 2
ECA/ECB
Group 6
ECA/ECB
Group 10
ECA/ECB
Group 14
ECA/ECB
Group 3
ECA/ECB
Group 7
ECA/ECB
Group 11
ECA/ECB
Group 15
ECA/ECB
Note:
Refer to Figure 3
for Echo Canceller
block diagram
V
DD2 (1.8V)
Ordering Information
MT93L00AB
100-Pin LQFP
MT93L00AV
208-Ball LBGA
-40
C to +85
C
DS5525
ISSUE 3
April 2002
MT93L00A
Multi-Channel Voice Echo Canceller
Preliminary Information
MT93L00A
Preliminary Information
2
Figure 2A - 100 Pin LQFP
3
1
3
0
5
0
1
7
1
1
9
7
2
5
2
3
2
1
1
9
3
5
1
3
1
5
1
D7
D6
D5
D4
D3
D2
D1
D0
CS
DS
VSS
NC
R/W
DTA
2
4
6
8
1
0
1
2
1
4
1
6
1
8
2
0
2
2
2
4
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
2
9
2
8
2
7
2
6
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
6
9
7
0
7
1
7
2
7
3
7
4
7
5
1
0
0
7
7
9
9
7
6
7
8
7
9
8
0
8
1
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
9
0
9
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
A
1
A
2
A
3
A
4
A
5
A
0
V
D
D
1
VDD2
NC
V
S
S
A
6
A
7
A
8
A
9
A
1
0
V
S
S
V
D
D
2
V
D
D
1
V
S
S
VSS
P
L
L
V
S
S
2
N
C
ODE
Sout
Rout
Sin
NC
NC
VSS
C4ib
Foib
Rin
VDD2
V
D
D
2
m
c
l
k
f
s
e
l
P
L
L
V
S
S
1
P
L
L
V
D
D
V
D
D
1
TMS
TDI
TDO
TCK
VSS
TRSTB
RESETB
IRQB
MT93L00AB
NC
(100 pin LQFP)
V
DD1
= 3.3V
V
DD2
= 1.8V
NC
V
D
D
1
V
S
S
N
C
N
C
NC
NC
NC
N
C
NC
N
C
N
C
N
C
N
C
N
C
N
C
N
C
N
C
N
C
N
C
N
C
N
C
IC0
IC0
IC0
IC0
I
C
0
IC0
IC0
IC0
IC0
I
C
0
I
C
0
I
C
0
I
C
0
I
C
0
I
C
0
N
C
Preliminary Information
MT93L00A
3
Figure 2B - 208 Ball LBGA
B
C
D
E
F
G
H
J
K
L
M
N
1
2
3
4
5
6
7
8
9
10
11
12
13
1
- A1 corner is identified by metallized markings.
A
14
15
16
P
R
T
1
V
DD2
c4i
F0i
Rin
Sin
Rout
ODE
A1
Sout
MCLK
Fsel
TMS
TDI
TCK
RESET
IRQ
DS
CS
R/W
DTA
D0
D1
D2
D4
D5
D6
D7
A10
A9
A8
A7
A6
A5
A4
A3
A2
MT93L00AV
V
DD1
ICO
PLLVSS PLLVDD
ICO
ICO
ICO
ICO
ICO
ICO
ICO
ICO
ICO
ICO
ICO
ICO
ICO
ICO
V
DD1
V
SS
NC
NC
TDO TRST
A0
D3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD2
V
DD2
V
DD2
V
DD2
V
DD2
V
DD2
V
DD2
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD1
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
MT93L00A
Preliminary Information
4
Pin Description
PIN #
PIN
Name
Description
208-Ball LBGA
100 PIN
LQFP
A1,A3,A7,A11,A13,A15,
A16,B2,B6,B8,B12,
B14,B15,B16,C3,C5,C7,
C9,C11,C12,C13,C14,
C16,
D4,D8,D10,D12,D13,E3,
E4,E14,F13,G3,G4,G7,G8,
G9,G10,H7,H8,H9,
H10,H13,H14,J7,J8,J9,
J10,K7,K8,K9,K10,K13,
K14,L3,L4,M13,M14,M15,
N3,N4,N5,N7,N9,N11,N13,
P2,P3,P5,P7,P9.P11,P13,
P14,R2,R14,R15,R16,T1,
T3,T7,T10, T14,T16
5, 18, 32,
42, 56, 69,
81, 98
V
SS
Ground.
A5,A9,B4,B10,C4,C8,C10,
D3,D5,D7,D9,D11,D14,E1
3,
F3,F4,F14,H3,H4,J13,J14,
L13,L14,M3,M4,N6,N8,
N10,N14,N15,P4,P6,P8,
P10,P15,R4,R6,R8,R10,
R12,T5,T12
27, 48, 77,
100
V
DD1
Positive Power Supply. Nominally 3.3 volt.
C6,D6,J3,J4,N12,P12,
G13,G14
14, 37,
64, 91
V
DD2
These pins should be wired to Vdd2= 1.8V.
E15,F15,A12,A10,A6,A2,
B1,B3,C1,C2,D2,E2,J2,K2,
R1
7,41,43,65,6
6,67,68,70,
71,72,86,87,
88,93,94
IC0
Internal Connection. These pins must be connected to V
SS
for
normal operation.
A14,C15,D1,D15,E1,F1,
G1,
G15,H1,H15,J1,J15,K1,
K15,L1,L15,F2,L2
24,25,26,44,
45,46,47,49,
51,52,53,54,
55,73,74,75,
76,78,79,80,
82,83,84,85,
89,99
NC
No connection. These pins must be left open for normal
operation.
R9
9
IRQ
Interrupt Request (Open Drain Output).
This output goes low
when an interrupt occurs in any channel. IRQ returns high when all the
interrupts have been read from the Interrupt FIFO Register. A pull-up
resistor (1K typical) is required at this output.
R11
10
DS
Data Strobe (Input). This active low input works in conjunction
with CS to enable the read and write operations.
R13
11
CS
Chip Select (Input). This active low input is used by a
microprocessor to activate the microprocessor port.
R5
12
R/W
Read/Write (Input). This input controls the direction of the data
bus lines (D7-D0) during a microprocessor access.
R7
13
DTA
Data Transfer Acknowledgment (Open Drain Output). This
active low output indicates that a data bus transfer is completed.
A pull-up resistor (1K typical) is required at this output.
Preliminary Information
MT93L00A
5
T2,T4,T6,T8,T9,T11,
T13,T15
15,16,17,
19,20,21,
22,23
D0 - D3,
D4 - D7
Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit
bidirectional data bus of the microprocessor port.
P16,N16,M16,L16,K16,
J16,H16,G16,F16,E16,
D16
28,29,30,31,
33,34,35,36,
38,39,40
A0 - A10
Address A0 to A10 (Input). These inputs provide the A10 - A0
address lines to the internal registers.
B13
57
ODE
Output Drive Enable (Input). This input pin is logically AND'd
with the ODE bit-6 of the Main Control Register. When both ODE
bit and ODE input pin are high, the Rout and Sout ST-BUS
outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the Rout
and Sout ST-BUS outputs are high impedance.
A8
58
Sout
Send PCM Signal Output (Output). Port 1 TDM data output
streams.
Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32
channels per stream.
B9
59
Rout
Receive PCM Signal Output (Output). Port 2 TDM data output
streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s
with 32 channels per stream.
B11
60
Sin
Send PCM Signal Input (Input). Port 2 TDM data input streams.
Sin pin receives serial TDM data streams at 2.048 Mb/s with 32
channels per stream.
B7
61
Rin
Receive PCM Signal Input (Input). Port 1 TDM data input
streams.
Rin pin receives serial TDM data streams at 2.048 Mb/s with 32
channels per stream.
B5
62
F0i
Frame Pulse (Input). This input accepts and automatically
identifies frame synchronization signals formatted according to
ST-BUS or GCI interface specifications.
A4
63
C4i
Serial Clock (Input). 4.096 MHz serial clock for shifting data in/
out on the serial streams (Rin, Sin, Rout, Sout).
G2
90
MCLK
Master Clock (Input). Nominal 10MHz or 20MHz Master Clock
input. May be connected to an asynchronous (relative to frame
signal) clock source.
H2
92
Fsel
Frequency select (Input). This input selects the Master Clock
frequency operation. When Fsel pin is low, nominal 19.2MHz
Master Clock input must be applied. When Fsel pin is high,
nominal 9.6MHz Master Clock input must be applied.
K3
95,97
PLLVss1
PLLVss2
PLL Ground. Must be connected to V
SS
K4
96
PLLV
DD
PLL Power Supply. Must be connected to V
DD2
M2
1
TMS
Test Mode Select (3.3V Input). JTAG signal that controls the
state transitions of the TAP controller. This pin is pulled high by
an internal pull-up when not driven.
Pin Description (continued)
PIN #
PIN
Name
Description
208-Ball LBGA
100 PIN
LQFP